[책][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
An architecture of a dataflow single chip processor
A highly parallel (more than a thousand) dataflow machine EM-4 is now under development.
The EM-4 design principle is to construct a high performance computer using a compact …
The EM-4 design principle is to construct a high performance computer using a compact …
Frequency and power correlation between at-speed scan and functional tests
S Sde-Paz, E Salomon - 2008 IEEE International Test …, 2008 - ieeexplore.ieee.org
At-speed scan is a key technique in modern IC testing. One of its drawbacks, with respect to
functional tests, is its excessive power consumption leading to voltage drop and frequency …
functional tests, is its excessive power consumption leading to voltage drop and frequency …
At-speed scan test with low switching activity
This paper presents a novel method to generate test vectors that mimic functional operation
from switching activity point of view. The method uses states obtained by applying a number …
from switching activity point of view. The method uses states obtained by applying a number …
Power-aware test: Challenges and solutions
S Ravi - 2007 IEEE International Test Conference, 2007 - ieeexplore.ieee.org
Power-aware test is increasingly becoming a major manufacturing test consideration due to
the problems of increased power dissipation in various test modes as well as test …
the problems of increased power dissipation in various test modes as well as test …
Power supply noise: A survey on effects and research
As technology scales to 32 nm and functional frequency and density continue to rise, PSN
effects, which can reduce a circuit's noise immunity and could lead to failures, pose new …
effects, which can reduce a circuit's noise immunity and could lead to failures, pose new …
A novel scheme to reduce power supply noise for high-quality at-speed scan testing
X Wen, K Miyase, S Kajihara, T Suzuki… - 2007 IEEE …, 2007 - ieeexplore.ieee.org
High-quality at-speed scan testing, characterized by high small-delay-defect detecting
capability, is indispensable to achieve high delay test quality for DSM circuits. However …
capability, is indispensable to achieve high delay test quality for DSM circuits. However …
Boosting ordinal features for accurate and fast iris recognition
In this paper, we present a novel iris recognition method based on learned ordinal features.
Firstly, taking full advantages of the properties of iris textures, a new iris representation …
Firstly, taking full advantages of the properties of iris textures, a new iris representation …
Deterministic clustering of incompatible test cubes for higher power-aware EDT compression
The embedded deterministic test-based compression uses cube merging to reduce a pattern
count, the amount of test data, and test time. It gradually expands a test pattern by …
count, the amount of test data, and test time. It gradually expands a test pattern by …
Modeling security-relevant data semantics
GW Smith - IEEE Transactions on Software Engineering, 1991 - search.proquest.com
A database system must have knowledge of the semantics of the data it manages in order to
accomplish its tasks. For a multilevel secure database system to provide effective multilevel …
accomplish its tasks. For a multilevel secure database system to provide effective multilevel …