Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …

Several interesting topologies emerge by incorporating the third dimension in networks-on-
chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC …

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides
achieved in 3-D manufacturing technologies. Advanced design methodologies for two …

This paper presents the first multiobjective microarchitectural floorplanning algorithm for
high-performance processors implemented in two-dimensional (2-D) and three-dimensional …

Three-dimensional (3-D) packaging via system-on-a-package (SOP) has been recently
proposed as an alternative solution to overcome the limitation of system-on-a-chip (SOC) …

In this paper, we present a performance and thermal-aware Steiner routing algorithm for
three-dimensional (3-D) stacked integrated circuits. Our algorithm consists of two steps: tree …

In current reconfigurable architectures, the interconnection structures increasingly contribute
more to the delay and power consumption. The demand for increased clock frequencies and …

Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active
devices, have the potential to dramatically enhance chip performance, functionality, and …

Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity
to solve the on-chip communication delays of next generation System-on-Chip (SoC) …

As technology advances, the interconnect delay among modules plays dominant role in chip
performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, is still …