A survey on the security of wired, wireless, and 3D network-on-chips
Network-on-Chips (NoCs) have been widely used as a scalable communication solution in
the design of multiprocessor system-on-chips (MPSoCs). NoCs enable communications …
the design of multiprocessor system-on-chips (MPSoCs). NoCs enable communications …
A survey on design approaches to circumvent permanent faults in networks-on-chip
Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …
MemPool: A shared-L1 memory many-core cluster with a low-latency interconnect
A key challenge in scaling shared-L1 multi-core clusters towards many-core (more than 16
cores) configurations is to ensure low-latency and efficient access to the L1 memory. In this …
cores) configurations is to ensure low-latency and efficient access to the L1 memory. In this …
SVM-based real-time hyperspectral image classifier on a manycore architecture
This paper presents a study of the design space of a Support Vector Machine (SVM)
classifier with a linear kernel running on a manycore MPPA (Massively Parallel Processor …
classifier with a linear kernel running on a manycore MPPA (Massively Parallel Processor …
Off-line map** of multi-rate dependent task sets to many-core platforms
This paper presents an approach to execute safety-critical applications on multi-and many-
core processors in a predictable manner. We investigate three concrete platforms: the Intel …
core processors in a predictable manner. We investigate three concrete platforms: the Intel …
On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms
Until the last decade, performance of HPC architectures has been almost exclusively
quantified by their processing power. However, energy efficiency is being recently …
quantified by their processing power. However, energy efficiency is being recently …
Efficient cache reconfiguration using machine learning in NoC-based many-core CMPs
Dynamic cache reconfiguration (DCR) is an effective technique to optimize energy
consumption in many-core architectures. While early work on DCR has shown promising …
consumption in many-core architectures. While early work on DCR has shown promising …
NMR-MPar: A fault-tolerance approach for multi-core and many-core processors
Featured Application The N-Modular Redundancy and M-Partitions (NMR-MPar) fault-
tolerance approach can be used to improve the reliability of embedded systems that are …
tolerance approach can be used to improve the reliability of embedded systems that are …
[BUCH][B] Heterogeneous computing architectures: Challenges and vision
Heterogeneous Computing Architectures: Challenges and Vision provides an updated
vision of the state-of-the-art of heterogeneous computing systems, covering all the aspects …
vision of the state-of-the-art of heterogeneous computing systems, covering all the aspects …
Seismic wave propagation simulations on low-power and performance-centric manycores
The large processing requirements of seismic wave propagation simulations make High
Performance Computing (HPC) architectures a natural choice for their execution. However …
Performance Computing (HPC) architectures a natural choice for their execution. However …