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[ספר][B] Fault-tolerance techniques for SRAM-based FPGAs
FL Kastensmidt, L Carro, RA da Luz Reis - 2006 - Springer
This book presents fault-tolerant techniques for programmable architectures, the well-known
Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming …
Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming …
SEU-tolerant QDI circuits [quasi delay-insensitive asynchronous circuits]
This paper addresses the issue of single-event upset (SEU) in quasi delay-insensitive (QDI)
asynchronous circuits. We show that an SEU can cause abnormal computations in QDI …
asynchronous circuits. We show that an SEU can cause abnormal computations in QDI …
A methodology for automatic insertion of selective TMR in digital circuits affected by SEUs
In this paper, a methodology to perform automatic selective TMR insertion on digital circuits
is presented, having as a constraint the required reliability level. Such reliability is …
is presented, having as a constraint the required reliability level. Such reliability is …
Soft error rate determination for nanometer CMOS VLSI logic
Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental
causes such as cosmic radiation and charged particles. These phenomena, also known as …
causes such as cosmic radiation and charged particles. These phenomena, also known as …
A parallel pipelined implementation of LOCO-I for JPEG-LS
We describe N2C-EX/sup 1/, a parallel, pipelined version of a modified LOCO-I lossless
compression algorithm used within the JPEG-LS coding scheme. This version takes into …
compression algorithm used within the JPEG-LS coding scheme. This version takes into …
DD1: a QDI, radiation-hard-by-design, near-threshold 18uW/MIPS microcontroller in 40nm bulk CMOS
This paper describes DD1, an asynchronous radiation-hard 8-bit AVR® microcontroller
(MCU) implemented in TSMC 40LP, a low-power bulk 40nm CMOS process. Designed for …
(MCU) implemented in TSMC 40LP, a low-power bulk 40nm CMOS process. Designed for …
Soft error mitigation in soft-core processors
Soft Error Mitigation in Soft-Core Processors | SpringerLink Skip to main content Advertisement
Springer Nature Link Account Menu Find a journal Publish with us Track your research Search …
Springer Nature Link Account Menu Find a journal Publish with us Track your research Search …
Modified triple modular redundancy structure based on asynchronous circuit technique
G Rui, C Wei, L Fang, D Kui… - 2006 21st IEEE …, 2006 - ieeexplore.ieee.org
Two modified triple modular redundancy (TMR) structures based on asynchronous circuit
technique are proposed in this paper. Double modular redundancy (DMR) structure uses …
technique are proposed in this paper. Double modular redundancy (DMR) structure uses …
Preserving hamming distance in arithmetic and logical operations
This paper presents a new method for fault-tolerant computing where for a given error rate, r,
the hamming distance between correct inputs and faulty inputs, as well as the hamming …
the hamming distance between correct inputs and faulty inputs, as well as the hamming …
Automatic insertion of selective TMR for SEU mitigation
RADECS 2008 Workshop Page 1 1 abstract² In this paper, a methodology is presented to
perform automatic selective TMR insertion on digital circuits, having as a constraint the required …
perform automatic selective TMR insertion on digital circuits, having as a constraint the required …