Inverse slope isolation and dual surface orientation integration
A semiconductor process and apparatus provide a high performance CMOS devices (108,
109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse …
109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse …
Monolithically integrated photodetectors
EA Fitzgerald - US Patent 7,705,370, 2010 - Google Patents
5,714,395 A 2, 1998 Bruel 5,810,924 A 9/1998 Legoues et al. 5,882,987 A 3, 1999
Srikrishnan 5,895.936 A 4/1999 Lee 6,039,803 A 3/2000 Fitzgerald et al. 6,107,653 A …
Srikrishnan 5,895.936 A 4/1999 Lee 6,039,803 A 3/2000 Fitzgerald et al. 6,107,653 A …
Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs
J Cai, X Chen, X Wang - US Patent 8,466,473, 2013 - Google Patents
A semiconductor device is provided that includes a semiconductor substrate having a well
region located within an upper region thereof. A semiconductor material stack is located on …
region located within an upper region thereof. A semiconductor material stack is located on …
Monolithically integrated silicon and III-V electronics
EA Fitzgerald - US Patent 8,120,060, 2012 - Google Patents
5,374,564 A 12/1994 Bruel 5,442,205 A 8, 1995 Brasen et al. 5,714,395 A 2, 1998 Bruel
5,760,426 A* 6/1998 Marx et al..................... 257 (190 5,810,924 A 9/1998 Legoues et al …
5,760,426 A* 6/1998 Marx et al..................... 257 (190 5,810,924 A 9/1998 Legoues et al …
Method for removing threshold voltage adjusting layer with external acid diffusion process
KJ Chen, RA Donaton, WS Huang, W Li - US Patent 8,227,307, 2012 - Google Patents
The present invention provides a method of forming a threshold Voltage adjusted gate stack
in which an external acid diffusion process is employed for selectively removing a portion of …
in which an external acid diffusion process is employed for selectively removing a portion of …
Embedded strain layer in thin SOI transistors and a method of forming the same
J Hoentschel, A Wei, M Horstmann… - US Patent 7,399,663, 2008 - Google Patents
By forming a deep recess through the buried insulating layer and re-growing a strained
semiconductor material, an enhanced strain generation mechanism may be provided in SOI …
semiconductor material, an enhanced strain generation mechanism may be provided in SOI …
Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate
metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid …
metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid …
Metal gate CMOS with at least a single gate metal and dual gate dielectrics
A complementary metal oxide semiconductor (CMOS) structure including at least one nFET
and at least one pFET located on a surface of a semiconductor substrate is provided. In …
and at least one pFET located on a surface of a semiconductor substrate is provided. In …
Monolithically integrated semiconductor materials and devices
EA Fitzgerald - US Patent 8,012,592, 2011 - Google Patents
B32B 9/00(2006.01) of relaxed silicon. The semiconductor structure further B32B
9/00(2006.01) includes an insulating layer disposed over the first monocrys HOIL …
9/00(2006.01) includes an insulating layer disposed over the first monocrys HOIL …
Semiconductor device structure with active regions having different surface directions and methods
Semiconductor structure and method to simultaneously achieve optimal stress type and
current flow for both nFET and pFET devices, and for gates orientated in one direction, are …
current flow for both nFET and pFET devices, and for gates orientated in one direction, are …