Reducing datacenter compute carbon footprint by harnessing the power of specialization: Principles, metrics, challenges and opportunities

T Eilam, P Bose, LP Carloni, A Cidon… - IEEE Transactions …, 2024 - ieeexplore.ieee.org
Computing is an indispensable tool in addressing climate change, but it also contributes to a
significant and steadily increasing carbon footprint, partly due to the exponential growth in …

Seizing the bandwidth scaling of on-package interconnect in a post-Moore's law world

G Chirkov, D Wentzlaff - … of the 37th International Conference on …, 2023 - dl.acm.org
The slowing and forecasted end of Moore's Law have forced designers to look beyond
simply adding transistors, encouraging them to employ other unused resources as a manner …

BlitzCoin: Fully Decentralized hardware power management for accelerator-rich SoCs

M Cochet, K Swaminathan, E Loscalzo… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
On-chip power-management techniques have evolved over several processor generations.
However, response time and scalability constraints have made it difficult to translate existing …

Mozart: Taming taxes and composing accelerators with shared-memory

V Suresh, B Mishra, Y **g, Z Zhu, N **… - Proceedings of the …, 2024 - dl.acm.org
Resource-constrained system-on-chips (SoCs) are increasingly heterogeneous with
specialized accelerators for various tasks. Acceleration taxes due to control and data …

RELIEF: Relieving Memory Pressure In SoCs Via Data Movement-Aware Accelerator Scheduling

S Gupta, S Dwarkadas - 2024 IEEE International Symposium …, 2024 - ieeexplore.ieee.org
Data movement latency when using on-chip accelerators in emerging heterogeneous
architectures is a serious performance bottleneck. While hardware/software mechanisms …

Resource demand analysis of IoT terminal chips based on atomic service modeling

Y Zhang, Y Nie, S Liu, J Li, Y Mao… - 2023 IEEE/IAS …, 2023 - ieeexplore.ieee.org
The diversity of smart city scenarios makes it difficult for Internet of Things terminals (IoTT) to
accurately match their differential demands for computing, storage, and communication …

Seamless Cache Extension for FPGA-based Multi-Core RISC-V SoC

A Kamaleldin, M Nickel, S Wu… - 2024 IEEE 37th …, 2024 - ieeexplore.ieee.org
Managing cache coherence is essential for optimizing computing performance and energy
efficiency in modern multi-/many-core systems. Enabling cache coherence in scalable agile …

Challenges and Opportunities in Future Multi-Chiplet Architectures

G Chirkov - 2024 - search.proquest.com
The slowdown of Moore's Law has decreased the rate that transistor density has been
increasing in silicon chips. These circumstances increasingly force computer architects to …

Efficient Tiling Architecture for Scalable CNN Inference: Leveraging High-Level Design and Embedded Scalable Platform (ESP)

DR Bueno Pacheco - 2023 - webthesis.biblio.polito.it
High-Level Design of Hardware Accelerators of Typical DNN LIn recent years, Convolutional
Neural Networks (CNNs) have gained significant prominence across a multitude of …

Hierarchical Architecture of 2D-CNN Accelerator: Leveraging High-Level Design and Embedded Scalable Platfrom (ESP)

A Marra - 2024 - webthesis.biblio.polito.it
POLITECNICO DI TORINO Page 1 POLITECNICO DI TORINO Master’s Degree in
Electronic Engineering Master’s Degree Thesis Hierarchical Architecture of a 2D-CNN …