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Uncovering in-dram rowhammer protection mechanisms: A new methodology, custom rowhammer patterns, and implications
The RowHammer vulnerability in DRAM is a critical threat to system security. To protect
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
Exploiting correcting codes: On the effectiveness of ecc memory against rowhammer attacks
Given the increasing impact of Rowhammer, and the dearth of adequate other hardware
defenses, many in the security community have pinned their hopes on error-correcting code …
defenses, many in the security community have pinned their hopes on error-correcting code …
Fine-grained DRAM: Energy-efficient DRAM for extreme bandwidth systems
Future GPUs and other high-performance throughput processors will require multiple TB/s of
bandwidth to DRAM. Satisfying this bandwidth demand within an acceptable energy budget …
bandwidth to DRAM. Satisfying this bandwidth demand within an acceptable energy budget …
TWiCe: Preventing row-hammering by exploiting time window counters
Computer systems using DRAM are exposed to row-hammer (RH) attacks, which can flip
data in a DRAM row without directly accessing a row but by frequently activating its adjacent …
data in a DRAM row without directly accessing a row but by frequently activating its adjacent …
TRiM: Enhancing processor-memory interfaces with scalable tensor reduction in memory
Personalized recommendation systems are gaining significant traction due to their industrial
importance. An important building block of recommendation systems consists of the …
importance. An important building block of recommendation systems consists of the …
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
DRAM cells in close proximity can fail depending on the data content in neighboring cells.
These failures are called data-dependent failures. Detecting and mitigating these failures …
These failures are called data-dependent failures. Detecting and mitigating these failures …
A survey of techniques for improving error-resilience of DRAM
Aggressive process scaling and increasing demands of performance/cost efficiency have
exacerbated the incidences and impact of errors in DRAM systems. Due to this …
exacerbated the incidences and impact of errors in DRAM systems. Due to this …
How to kill the second bird with one ecc: The pursuit of row hammer resilient dram
Error-correcting code (ECC) has been widely used in DRAM-based memory systems to
address the exacerbating random errors following the fabrication process scaling. However …
address the exacerbating random errors following the fabrication process scaling. However …
Bit-exact ECC recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …
Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines
DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …