Uncovering in-dram rowhammer protection mechanisms: A new methodology, custom rowhammer patterns, and implications

H Hassan, YC Tugrul, JS Kim, V Van der Veen… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
The RowHammer vulnerability in DRAM is a critical threat to system security. To protect
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …

Exploiting correcting codes: On the effectiveness of ecc memory against rowhammer attacks

L Cojocar, K Razavi, C Giuffrida… - 2019 IEEE Symposium …, 2019 - ieeexplore.ieee.org
Given the increasing impact of Rowhammer, and the dearth of adequate other hardware
defenses, many in the security community have pinned their hopes on error-correcting code …

Fine-grained DRAM: Energy-efficient DRAM for extreme bandwidth systems

M O'Connor, N Chatterjee, D Lee, J Wilson… - Proceedings of the 50th …, 2017 - dl.acm.org
Future GPUs and other high-performance throughput processors will require multiple TB/s of
bandwidth to DRAM. Satisfying this bandwidth demand within an acceptable energy budget …

TWiCe: Preventing row-hammering by exploiting time window counters

E Lee, I Kang, S Lee, GE Suh, JH Ahn - Proceedings of the 46th …, 2019 - dl.acm.org
Computer systems using DRAM are exposed to row-hammer (RH) attacks, which can flip
data in a DRAM row without directly accessing a row but by frequently activating its adjacent …

TRiM: Enhancing processor-memory interfaces with scalable tensor reduction in memory

J Park, B Kim, S Yun, E Lee, M Rhu… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Personalized recommendation systems are gaining significant traction due to their industrial
importance. An important building block of recommendation systems consists of the …

Detecting and mitigating data-dependent DRAM failures by exploiting current memory content

S Khan, C Wilkerson, Z Wang, AR Alameldeen… - Proceedings of the 50th …, 2017 - dl.acm.org
DRAM cells in close proximity can fail depending on the data content in neighboring cells.
These failures are called data-dependent failures. Detecting and mitigating these failures …

A survey of techniques for improving error-resilience of DRAM

S Mittal, MS Inukonda - Journal of Systems Architecture, 2018 - Elsevier
Aggressive process scaling and increasing demands of performance/cost efficiency have
exacerbated the incidences and impact of errors in DRAM systems. Due to this …

How to kill the second bird with one ecc: The pursuit of row hammer resilient dram

MJ Kim, M Wi, J Park, S Ko, J Choi, H Nam… - Proceedings of the 56th …, 2023 - dl.acm.org
Error-correcting code (ECC) has been widely used in DRAM-based memory systems to
address the exacerbating random errors following the fabrication process scaling. However …

Bit-exact ECC recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics

M Patel, JS Kim, T Shahroodi… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …

Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines

J Kim, M Patel, H Hassan… - 2018 IEEE 36th …, 2018 - ieeexplore.ieee.org
DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …