Recent trend of FinFET devices and its challenges: A review

RS Pal, S Sharma, S Dasgupta - 2017 Conference on …, 2017 - ieeexplore.ieee.org
Recent technological demand of FinFETs have been explored and reviewed in this work.
The downscaling of the conventional MOSFET urge to the researchers to innovate new …

Leakage current calculation for PV inverter system based on a parasitic capacitor model

W Chen, X Yang, W Zhang… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
The occurrence of leakage current that can occur in photovoltaic (PV) system depends
strongly on the value of parasitic capacitance between PV panel and the ground. However …

[HTML][HTML] S2DS: Physics-based compact model for circuit simulation of two-dimensional semiconductor devices including non-idealities

SV Suryavanshi, E Pop - Journal of Applied Physics, 2016 - pubs.aip.org
We present a physics-based compact model for two-dimensional (2D) field-effect transistors
(FETs) based on monolayer semiconductors such as MoS 2. A semi-classical transport …

A detailed investigation of dielectric-modulated dual-gate TMD FET based label-free biosensor via analytical modelling

M Kumari, NK Singh, M Sahoo - Scientific Reports, 2022 - nature.com
In this work, an analytical model is developed for DM-DG-TMD-FET-based Biosensor
including Fringing-field effects. The Analytical model has been developed for two different …

Designing Power-Efficient Transistors Using Narrow-Bandwidth Materials from the (; ; ) Monolayer Series

K Nandan, S Bhowmick, YS Chauhan, A Agarwal - Physical Review Applied, 2023 - APS
The subthreshold leakage current in transistors has become a critical limiting factor for
realizing ultralow-power transistors. The leakage current is predominantly dictated by the …

Frequency-independent self-powered sensing based on capacitive impedance matching effect of triboelectric nanogenerator

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A Bansal, BC Paul, K Roy - IEEE Transactions on Computer …, 2006 - ieeexplore.ieee.org
An analytical model is proposed to compute the fringe capacitance between two
nonoverlap** interconnects in different layers using a conformal map** technique. With …

Analysis of geometry-dependent parasitics in multifin double-gate FinFETs

W Wu, M Chan - IEEE Transactions on Electron Devices, 2007 - ieeexplore.ieee.org
This paper analyzes the geometry-dependent parasitic components in multifin double-gate
fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance …

Impact of a process variation on nanowire and nanotube device performance

BC Paul, S Fujita, M Okajima, TH Lee… - … on Electron Devices, 2007 - ieeexplore.ieee.org
In this paper, we present an in-depth analysis of the nanowire and nanotube device
performance under process variability. Although every process parameter variation …

Impact of High- Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

CR Manoj, VR Rao - IEEE electron device letters, 2007 - ieeexplore.ieee.org
The impact of high-k gate dielectrics on device short-channel and circuit performance of fin
field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed …