In high volume manufacturing, conventional approach to deal with inverse-temperature
dependence (ITD) and aging is to add a post silicon flat voltage guard band to all dies based …

This paper presents iRazor, a lightweight error detection and correction approach, to
suppress the cycle time margin that is traditionally added to very large scale integration …

Variability in device, circuit, and system parameters is one of the primary challenges in the
semiconductor industry. Parameter variations degrade processor performance, energy …

This paper aims to take stock of recent advances in the field of energy-quality (EQ) scalable
circuits and systems, as promising direction to continue the historical exponential energy …

In this paper, the concept of energy-quality (EQ) scalable systems is introduced and
explored, as novel design dimension to scale down energy in integrated systems for the …

Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess
timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed …

This brief surveys the past 20 years of near/sub-threshold digital integrated circuit design.
Most of the chips have been highly characterized for voltage scaling down to near/sub …

In this paper, a novel framework is introduced to estimate the max-delay variability in logic
paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of …

This paper introduces dynamically adaptable pipelines to enable microarchitecture-driven
voltage scaling, adapting the microarchitecture to the most energy-efficient configuration for …

This paper presents an instruction-driven adaptive clock management scheme using a
dynamic phase scaling (DPS) operation and compiler-assisted cross-layer design …