Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT
P Batude, L Clavelier, MA Jaud, O Thomas… - US Patent …, 2012 - Google Patents
(57) ABSTRACT A microelectronic device including: a substrate surmounted by a stack of
layers, at least one first transistor situated at a given level of said stack, at least one second …
layers, at least one first transistor situated at a given level of said stack, at least one second …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Method for fabrication of a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Semiconductor system and device
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 9,219,005, 2015 - Google Patents
US9219005B2 - Semiconductor system and device - Google Patents US9219005B2 -
Semiconductor system and device - Google Patents Semiconductor system and device …
Semiconductor system and device - Google Patents Semiconductor system and device …
Integrated circuit device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 9,099,526, 2015 - Google Patents
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Integrated circuit device and structure - Google Patents Integrated circuit device and structure …
Integrated circuit device and structure - Google Patents Integrated circuit device and structure …
3D semiconductor device and structure
Z Or-Bach, B Cronquist - US Patent 10,840,239, 2020 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
3D integrated circuit with logic
Z Or-Bach, Z Wurman - US Patent 8,492,886, 2013 - Google Patents
Related US Application Data WO PCT/US2008/063483 5, 2008 (63) Continuation-in-part of
application No. 12/706.520, OTHER PUBLICATIONS filed on Feb. 16, 2010, and a …
application No. 12/706.520, OTHER PUBLICATIONS filed on Feb. 16, 2010, and a …
3D semiconductor device and structure with back-bias
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2015 - Google Patents
H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state
devices during manufacture or treatment thereof; Apparatus specially adapted for handling …
devices during manufacture or treatment thereof; Apparatus specially adapted for handling …