Reliable intersection protocols using vehicular networks
Autonomous driving will play an important role in the future of transportation. Various
autonomous vehicles have been demonstrated at the DARPA Urban Challenge [3]. General …
autonomous vehicles have been demonstrated at the DARPA Urban Challenge [3]. General …
Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level
O Mbarek, A Pegatoquet, M Auguin - IET Circuits, Devices & Systems, 2012 - IET
Building efficient and correct system power-management strategies relies on efficient power
architecture decision making as well as respecting structural dependencies induced by such …
architecture decision making as well as respecting structural dependencies induced by such …
Formal verification of architectural power intent
This paper presents a verification framework that attempts to bridge the disconnect between
high-level properties capturing the architectural power management strategy and the …
high-level properties capturing the architectural power management strategy and the …
A methodology for power-aware transaction-level models of systems-on-chip using UPF standard concepts
O Mbarek, A Pegatoquet, M Auguin - Integrated Circuit and System Design …, 2011 - Springer
Building efficient and correct system power management strategies relies on efficient power
architecture decision-making as well as respecting structural dependencies induced by such …
architecture decision-making as well as respecting structural dependencies induced by such …
Power specification, simulation and verification of SystemC designs
K Gagarski, M Petrov, M Moiseev… - 2016 IEEE East-West …, 2016 - ieeexplore.ieee.org
SystemC language is widely used for hardware modules and whole systems on chip
development. Hardware development for low power applications requires power …
development. Hardware development for low power applications requires power …
POWER-TRUCTOR: An integrated tool flow for formal verification and coverage of architectural power intent
With the growing complexity and gradually shrinking power requirements in the system-on-
chip designs, sophisticated global power management policies (which orchestrate the …
chip designs, sophisticated global power management policies (which orchestrate the …
Energy efficient implementation, power aware simulation and verification of 16-bit ALU using unified power format standards
With the increase in the demand for high performance and high speed VLSI systems such as
network processors in networking or SOCs in communication and computing has shifted the …
network processors in networking or SOCs in communication and computing has shifted the …
Architectural low-power design using transaction-based system modeling and simulation
F Mischkalla, W Mueller - 2014 international conference on …, 2014 - ieeexplore.ieee.org
Energy efficiency drives the development of more and more complex low-power designs.
Based on dynamic power management techniques, multiple voltage islands as well as a …
Based on dynamic power management techniques, multiple voltage islands as well as a …
Approach for a unified functional verification flow
A Hany, A Ismail, A Kamal… - 2013 Saudi International …, 2013 - ieeexplore.ieee.org
This paper proposes a unified flow for functional verification using assertion-based and
coverage-based verification techniques. For each technique, both simulation and formal …
coverage-based verification techniques. For each technique, both simulation and formal …
Specification and formal verification of power gating in processors
This paper presents a method for specification as well as efficient formal verification of
power gating feature of processors. Given an instruction-set architecture model of a …
power gating feature of processors. Given an instruction-set architecture model of a …