Insulators for 2D nanoelectronics: the gap to bridge

YY Illarionov, T Knobloch, M Jech, M Lanza… - Nature …, 2020 - nature.com
Nanoelectronic devices based on 2D materials are far from delivering their full theoretical
performance potential due to the lack of scalable insulators. Amorphous oxides that work …

Charge transport and mobility engineering in two-dimensional transition metal chalcogenide semiconductors

SL Li, K Tsukagoshi, E Orgiu, P Samorì - Chemical Society Reviews, 2016 - pubs.rsc.org
Two-dimensional (2D) van der Waals semiconductors represent the thinnest, air stable
semiconducting materials known. Their unique optical, electronic and mechanical properties …

Scaling carbon nanotube complementary transistors to 5-nm gate lengths

C Qiu, Z Zhang, M **ao, Y Yang, D Zhong, LM Peng - Science, 2017 - science.org
High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate
length of 5 nanometers can be fabricated that perform better than silicon complementary …

Vasculature and lymphatic system imaging and ablation associated with a reservoir

RA Hyde, EKY Jung, NP Myhrvold… - US Patent …, 2012 - Google Patents
Filed: Oct. 5, 2007(57) In an embodiment, a system includes one or one or more (65) Prior
Publication Data reservoirs responsive to control circuitry for receiving US 2009/0093728A1 …

Silicon device scaling to the sub-10-nm regime

M Ieong, B Doris, J Kedzierski, K Rim, M Yang - Science, 2004 - science.org
In the next decade, advances in complementary metal-oxide semiconductor fabrication will
lead to devices with gate lengths (the region in the device that switches the current flow on …

Challenges for nanoscale MOSFETs and emerging nanoelectronics

YB Kim - transactions on electrical and electronic materials, 2010 - koreascience.kr
Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main
key for continuous progress in silicon-based semiconductor industry over the past three …

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

KP Pradhan, SK Mohapatra, PK Sahu… - Microelectronics journal, 2014 - Elsevier
Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide
(SiO 2) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt …

A proposal on an optimized device structure with experimental studies on recent devices for the DRAM cell transistor

MJ Lee, S **, CK Baek, SM Hong… - … on Electron Devices, 2007 - ieeexplore.ieee.org
We have experimentally analyzed the leakage mechanism and device degradations caused
by the Fowler–Nordheim (F–N) and hot carrier stresses for the recently developed dynamic …

Predictive technology model for nano-CMOS design exploration

W Zhao, Y Cao - ACM Journal on Emerging Technologies in Computing …, 2007 - dl.acm.org
A predictive MOSFET model is critical for early circuit design research. In this work, a new
generation of Predictive Technology Model (PTM) is developed, covering emerging physical …

Pulsed high-density plasmas for advanced dry etching processes

S Banna, A Agarwal, G Cunge, M Darnon… - Journal of Vacuum …, 2012 - pubs.aip.org
Plasma etching processes at the 22 nm technology node and below will have to satisfy
multiple stringent scaling requirements of microelectronics fabrication. To satisfy these …