High performance stress-enhanced MOSFETs using Si: C and SiGe epitaxial source/drain and method of manufacture
(57) ABSTRACT A semiconductor device and method of manufacturing a semiconductor
device. The semiconductor device includes channels for a pFET and annFET. A SiGe layer …
device. The semiconductor device includes channels for a pFET and annFET. A SiGe layer …
Device with stepped source/drain region profile
G Curello, B Sell, S Tyagi, C Auth - US Patent 7,335,959, 2008 - Google Patents
(56) References Cited stepped source and drain regions. The stepped regions may US
PATENT DOCUMENTS provide significant strain in a channel region while mini mizing …
PATENT DOCUMENTS provide significant strain in a channel region while mini mizing …
High performance strained channel MOSFETs by coupled stress effects
CH Chang, W Chang, CY Fu - US Patent 7,119,404, 2006 - Google Patents
Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS
device performance without substantially degrading PMOS device performance and method …
device performance without substantially degrading PMOS device performance and method …
Advanced forming method and structure of local mechanical strained transistor
CH Chen, TL Lee - US Patent 7,935,587, 2011 - Google Patents
Embodiments of the invention provide a semiconductor fab rication method and a structure
for strained transistors. A method comprises forming a stressor layer over a MOS tran sistor …
for strained transistors. A method comprises forming a stressor layer over a MOS tran sistor …
Selective stress relaxation of contact etch stop layer through layout design
LW Teo, E Quek, DK Sohn - US Patent 7,888,214, 2011 - Google Patents
A structure and method of fabrication of a semiconductor device, where a stress layer is
formed over a MOS transistor to put either tensile stress or compressive stress on the …
formed over a MOS transistor to put either tensile stress or compressive stress on the …
Selective spacer formation on transistors of different classes on the same device
G Curello, IR Post, CH Jan, M Bohr - US Patent 7,541,239, 2009 - Google Patents
A method of selectively forming a spacer on a first class of transistors and devices formed by
such methods. The method can include depositing a conformal first deposition layer on a …
such methods. The method can include depositing a conformal first deposition layer on a …
Method for forming integrated advanced semiconductor device using sacrificial stress layer
JW Hsu, MH Tsai, CH Chen, YC Huang - US Patent 7,223,647, 2007 - Google Patents
(54) METHOD FOR FORMING INTEGRATED 6,563,152 B2 5/2003 Roberds et al.
ADVANCED SEMCONDUCTOR DEVICE 6,939,814 B2* 9/2005 Chan et al …
ADVANCED SEMCONDUCTOR DEVICE 6,939,814 B2* 9/2005 Chan et al …
Stress engineering for cap layer induced stress
V Moroz, D Pramanik - US Patent App. 11/379,548, 2007 - Google Patents
BACKGROUND 0001. The invention relates to methods for improving integrated circuit
performance through stress-engineering relative to a strained cap layer of the device, and …
performance through stress-engineering relative to a strained cap layer of the device, and …
Selective CESL structure for CMOS application
CL Chen, MJ Chen, JJ Wang - US Patent 7,696,578, 2010 - Google Patents
A PMOS device less affected by negative bias time instability (NBTI) and a method for
forming the same are provided. The PMOS device includes a barrier layer over at least a …
forming the same are provided. The PMOS device includes a barrier layer over at least a …
Double anneal with improved reliability for dual contact etch stop liner scheme
KY Lim, V Chan, EH Lim, W Lin, JF Fen - US Patent 7,615,433, 2009 - Google Patents
A method for forming a device with both PFET and NFET transistors using a PFET
compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a …
compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a …