A high performance binary to BCD converter for decimal multiplication
J Bhattacharya, A Gupta, A Singh - Proceedings of 2010 …, 2010 - ieeexplore.ieee.org
Decimal data processing applications have grown exponentially in recent years thereby
increasing the need to have hardware support for decimal arithmetic. Binary to BCD …
increasing the need to have hardware support for decimal arithmetic. Binary to BCD …
Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding
This paper proposes efficient implementations for addition/subtraction based on decimal
floating point with Densely Packed Decimal (DPD) and Binary Integer Decimal (BID) …
floating point with Densely Packed Decimal (DPD) and Binary Integer Decimal (BID) …
Decimal addition on FPGA based on a mixed BCD/excess-6 representation
Decimal arithmetic has recovered the attention in the field of computer arithmetic due to
decimal precision requirements of application domains like financial, commercial and …
decimal precision requirements of application domains like financial, commercial and …
A high performance unified BCD and binary adder/subtractor
Decimal data processing applications have grown exponentially in recent years thereby
increasing the need to have hardware support for decimal arithmetic. In this paper, an …
increasing the need to have hardware support for decimal arithmetic. In this paper, an …
4: 2 and 5: 2 Decimal Compressors
Decimal compressors are essential components for partial product addition facilitating
decimal multipliers. In this paper improved design and architectures of 4: 2 and 5: 2 high …
decimal multipliers. In this paper improved design and architectures of 4: 2 and 5: 2 high …
Delay optimized binary to BCD converter for multi-operand parallel decimal adder
G Ragunath, V Sugandh… - … conference on vision …, 2019 - ieeexplore.ieee.org
Decimal arithmetic is receiving greater attention due to its applications in banking and
internet-based sectors. Several algorithms have been introduced for Multi-operand addition …
internet-based sectors. Several algorithms have been introduced for Multi-operand addition …
Proposal for fast BCD addition
Decimal Arithmetic Hardware Research accelerated phenomenally in the last decade with
introduction of Decimal Floating Point formats in IEEE 754-2008.Addition'being one of the …
introduction of Decimal Floating Point formats in IEEE 754-2008.Addition'being one of the …
FPGA-specific decimal sign-magnitude addition and subtraction
The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-
2008 standard, where the significand in floating-point numbers is coded as SM. However …
2008 standard, where the significand in floating-point numbers is coded as SM. However …
Fast binary to BCD converters for decimal communications using new recoding circuits
TB Juang, YM Chiu - 2014 International Symposium on …, 2014 - ieeexplore.ieee.org
In this work, fast binary to binary-coded-decimal (BCD) code converters for decimal
communications are proposed. By employing new recoding circuits, our proposed …
communications are proposed. By employing new recoding circuits, our proposed …
Addition of BCD digits using non-standard codes
C Coulston, V Dave - CONIELECOMP 2012, 22nd International …, 2012 - ieeexplore.ieee.org
Decimal arithmetic is gaining prominence in many commercial applications where a high
degree of accuracy is desired. Some of these include currency conversion and internet …
degree of accuracy is desired. Some of these include currency conversion and internet …