EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms

C Pilato, S Bohm, F Brocheton… - … , Automation & Test …, 2021 - ieeexplore.ieee.org
High-Performance Big Data Analytics (HPDA) applications are characterized by huge
volumes of distributed and heterogeneous data that require efficient computation for …

High level synthesis of RDF queries for graph analytics

VG Castellana, M Minutoli, A Morari… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
In this paper we present a set of techniques that enable the synthesis of efficient custom
accelerators for memory intensive, irregular applications. To address the challenges of …

System-level memory optimization for high-level synthesis of component-based SoCs

C Pilato, P Mantovani, G Di Guglielmo… - Proceedings of the 2014 …, 2014 - dl.acm.org
The design of specialized accelerators is essential to the success of many modern Systems-
on-Chip. Electronic system-level design methodologies and high-level synthesis tools are …

An automated flow for the high level synthesis of coarse grained parallel applications

VG Castellana, F Ferrandi - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
High Level Synthesis (HLS) provides a way to significantly enhance the productivity of
embedded system designers, by enabling the automatic or semiautomatic generation of …

Exploring the energy efficiency of multispeculative adders

AA Del Barrio, R Hermida… - 2013 IEEE 31st …, 2013 - ieeexplore.ieee.org
Variable Latency Adders are attracting strong interest for increasing performance at a low
cost. However, most of the literature is focused on achieving a good area-delay tradeoff. In …

Scheduling independent liveness analysis for register binding in high level synthesis

VG Castellana, F Ferrandi - 2013 Design, Automation & Test in …, 2013 - ieeexplore.ieee.org
Classical techniques for register allocation and binding require the definition of the program
execution order, since a partial ordering relation between operations must be induced to …

Speeding-up memory intensive applications through adaptive hardware accelerators

VG Castellana, F Ferrandi - 2012 SC Companion: High …, 2012 - ieeexplore.ieee.org
Heterogeneous architectures are becoming an increasingly relevant component for High-
Performance Computing: they combine the computational power of multi-core processors …

Accelerator design with high-level synthesis

C Pilato, S Soldavini - Handbook of Computer Architecture, 2024 - Springer
Specialized accelerators can exploit spatial parallelism on both operations and data thanks
to a dedicated microarchitecture with a better use of the hardware resources. Designers …

Variable latency request arbitration

JB Mirza, Q Ma, LKN Lai - US Patent 10,915,359, 2021 - Google Patents
(57) ABSTRACT A technique for scheduling processing tasks having different latencies is
provided. The technique involves identifying one or more available requests in a request …

[PDF][PDF] Extending distributed control for high-level synthesis beyond borders of basic blocks

M Shimizu, N Ishiura - Proc. SASIMI 2016, 2016 - ist.ksc.kwansei.ac.jp
This paper proposes an extension of distributed control, which enables efficient run-time
scheduling of variable latency operations, to multiple dataflow graphs. Conventional high …