Driven by the need to reduce the power consumption of mobile devices, and servers/data
centers, and yet continue to deliver improved performance and experience by the end …

The Cu-filling process in through-silicon via (TSV-Cu) is a key technology for chip stacking
and three-dimensional vertical packaging. During this process, defects resulting from …

The through-silicon via (TSV) approach is essential for 3-D integrated circuit (3-DIC)
packaging technology. TSV fabrication process, however, is still facing several challenges …

In this article, we propose and analyze a through silicon via (TSV) with a silicon dioxide well
(SDW) to reduce leakage current in the design of a high-speed signaling and low-power …

In this article, a high-efficient design method of through silicon via (TSV) array for thermal
management of 3-dimensional (3-D) integrated system is developed based on the …

In the post-Moore era, advanced electronic packaging technology emerges as a prominent
direction for the future evolution of semiconductor industry. Nevertheless, warpage remains …

For Wafer to Wafer Hybrid Bonding (W2W-HB) technology, warpage mitigation and precise
Cu to Cu bonding are required to ensure a robust bonding integrity. This paper documents a …

This paper provides an overview of 3D detectors fabrication technology developed in the
clean room of the Microelectronics Institute of Barcelona (IMB-CNM). Emphasis is put on …

A six-side molded wafer-level chip scale package (mWLCSP) is a novel and attractive
packaging method for smart phone applications due to its lower cost, better electrical …

In this study, fan-out panel-level packaging (FO-PLP) technology using a redistribution layer
(RDL) first approach is demonstrated using a large glass panel as a carrier (550 mm× 650 …