A review on performance comparison of advanced MOSFET structures below 45 nm technology node

N Mendiratta, SL Tripathi - Journal of Semiconductors, 2020 - iopscience.iop.org
CMOS technology is one of the most frequently used technologies in the semiconductor
industry as it can be successfully integrated with ICs. Every two years the number of MOS …

18nm n-channel and p-channel Do**less asymmetrical Junctionless DG-MOSFET: low power CMOS based digital and memory applications

N Mendiratta, SL Tripathi - Silicon, 2022 - Springer
In this paper, an 18nm do**less asymmetrical junctionless (AJ) double gate (DG)
MOSFET has been designed for suppressed short channel effects (SCEs) for low power …

[PDF][PDF] Advanced MOSFET Technologies for Next Generation Communication Systems-Perspective and Challenges: A Review.

H Sood, VM Srivastava, G Singh - Journal of Engineering Science & …, 2018 - academia.edu
In this review, authors have retrospect the state-of-art dimension scaling and emerging other
non-conventional MOSFET structures particularly, the Double-Gate (DG) MOSFET and …

[HTML][HTML] Analytical study of dual material surrounding gate MOSFET to suppress short-channel effects (SCEs)

A Pal, A Sarkar - Engineering Science and Technology, an International …, 2014 - Elsevier
In this paper, a 2D analytical model for the Dual Material Surrounding Gate MOSFET
(DMSG) by solving the Poisson equation has been proposed and verified using ATLAS …

Nanowire array-based MOSFET for future CMOS technology to attain the ultimate scaling limit

K Bhol, U Nanda - Silicon, 2022 - Springer
Silicon nanowire (SiNW) structures are the essential foundations of the next generation
highly efficient and lowcost electronic devices because of their specific chemical, optical …

Numerical modeling of subthreshold region of junctionless double surrounding gate MOSFET (JLDSG)

S Rewari, S Haldar, V Nath, SS Deswal… - Superlattices and …, 2016 - Elsevier
Abstract In this paper, Numerical Model for Electric Potential, Subthreshold Current and
Subthreshold Swing for Junctionless Double Surrounding Gate (JLDSG) MOSFEThas been …

Channel length scaling pattern for cylindrical surrounding double-gate (CSDG) MOSFET

MA Uchechukwu, VM Srivastava - IEEE access, 2020 - ieeexplore.ieee.org
The natural length of MOSFETs helps to describe the potential distribution in the Silicon
substrate. This natural length varies in different device structures, from a single gate to multi …

A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance

S Dash, GP Mishra - Advances in Natural Sciences …, 2015 - iopscience.iop.org
A 2D analytical tunnel field-effect transistor (FET) potential model with cylindrical gate (CG-
TFET) based on the solution of Laplace's equation is proposed. The band-to-band tunneling …

Design and Analysis of InP/InAs/AlGaAs Based Cylindrical Surrounding Double-Gate (CSDG) MOSFETs With La2O3 for 5-nm Technology

P Paramasivam, N Gowthaman, VM Srivastava - IEEE Access, 2021 - ieeexplore.ieee.org
The structural improvement and rapid production of InP, InAs (III-V, binary), and AlGaAs (III-
V, ternary) compound semiconductor materials have invariably enabled its utilization in …

Capacitive modeling of cylindrical surrounding double-gate MOSFETs for hybrid RF applications

N Gowthaman, VM Srivastava - IEEE Access, 2021 - ieeexplore.ieee.org
The advancements in semiconductor technology greatly impact the growth of hybrid VLSI
devices and components. The nanometer technology has been possibly executed due to the …