0.7-V three-stage class-AB CMOS operational transconductance amplifier
A simple high-performance architecture for bulk-driven operational transconductance
amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single …
amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single …
A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI
This work demonstrates a fully-integrated, compact body-bias generator (BBG) with a fine
voltage step and sub-100ns response time for use in process and voltage compensation as …
voltage step and sub-100ns response time for use in process and voltage compensation as …
A FoM for investigation of SB TFET biosensor considering non-ideality
A new FoM to investigate a carefully engineered Schottky barrier (SB) TFET by accounting
for dc power consumption, and silicon area, which are the key consideration for energy …
for dc power consumption, and silicon area, which are the key consideration for energy …
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for
low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully …
low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully …
Time and rate dependent synaptic learning in neuro-mimicking resistive memories
Memristors have demonstrated immense potential as building blocks in future adaptive
neuromorphic architectures. Recently, there has been focus on emulating specific synaptic …
neuromorphic architectures. Recently, there has been focus on emulating specific synaptic …
Dual mode logic—Design for energy efficiency and high performance
The recently proposed dual mode logic (DML) gates family enables a very high level of
energy-delay optimization flexibility at the gate level. In this paper, this flexibility is utilized to …
energy-delay optimization flexibility at the gate level. In this paper, this flexibility is utilized to …
Novel self-body-biasing and statistical design for near-threshold circuits with ultra energy-efficient AES as case study
Near-threshold operation enables high energy efficiency, but requires proper design
techniques to deal with performance loss and increased sensitivity to process variations. In …
techniques to deal with performance loss and increased sensitivity to process variations. In …
Digital systems power management for high performance mixed signal platforms
A Kapoor, C Groot, GV Piqué, H Fatemi… - … on Circuits and …, 2014 - ieeexplore.ieee.org
High performance mixed signal (HPMS) platforms require stringent overall system and
subsystem performance. The ability to design ultra-low power systems is used in a wide …
subsystem performance. The ability to design ultra-low power systems is used in a wide …
Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range
X Deng, Y Mo - Electronics Letters, 2015 - Wiley Online Library
A new boost bulk‐driven sense‐amplifier‐based flip‐flop (BBDSAFF) is presented. First,
thanks to the boost and bulk‐driven technique, the BBDSAFF consumes much lower power …
thanks to the boost and bulk‐driven technique, the BBDSAFF consumes much lower power …
Component Dependencies Based Network-on-Chip Test
L Huang, T Zhao, Z Wang, J Zhan… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
On-line test of NoC is essential for its reliability. This paper proposed an integral test solution
for on-line test of NoC to reduce the test cost and improve the reliability of NOC. The test …
for on-line test of NoC to reduce the test cost and improve the reliability of NOC. The test …