We report on the process for formal concurrency modelling at Arm. An initial formal
consistency model of the Arm achitecture, written in the cat language, was published and …

We have developed and mechanically verified an ML system called CakeML, which
supports a substantial subset of Standard ML. CakeML is implemented as an interactive …

We propose an axiomatic generic framework for modelling weak memory. We show how to
instantiate this framework for Sequential Consistency (SC), Total Store Order (TSO), C++ …

Exploiting the multiprocessors that have recently become ubiquitous requires high-
performance and reliable concurrent systems code, for concurrent data structures, operating …

Shared-memory concurrency in C and C++ is pervasive in systems programming, but has
long been poorly defined. This motivated an ongoing shared effort by the standards …

The future of mobile telephony is expected to rely on mobile services and the use of mobile
services will be an integral part of the revenues to be generated by third generation mobile …

Real multiprocessors do not provide the sequentially consistent memory that is assumed by
most work on semantics and verification. Instead, they have relaxed memory models …

ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and
ARMv8. Over time, and partly due to work building formal semantics for ARM concurrency, it …

Exploiting today's multiprocessors requires high-performance and correct concurrent
systems code (optimising compilers, language runtimes, OS kernels, etc.), which in turn …

In this paper we develop semantics for key aspects of the ARMv8 multiprocessor
architecture: the concurrency model and much of the 64-bit application-level instruction set …