A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon
Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike
conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less …
conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less …
A survey describing beyond Si transistors and exploring their implications for future processors
The advancement of Silicon CMOS technology has led information technology innovation for
decades. However, scaling transistors down according to Moore's law is almost reaching its …
decades. However, scaling transistors down according to Moore's law is almost reaching its …
Power-efficient heterogeneous many-core design with ncfet technology
Multi-/many-core, homogeneous or heterogeneous architectures, using the existing CMOS
technology are inevitably approaching the limit of attainable power efficiency due to the …
technology are inevitably approaching the limit of attainable power efficiency due to the …
An ultra-Low power MoS2 tunnel field effect transistor PLL design for IoT applications
NO Adesina, A Srivastava, AU Khan… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
This work presents the implementation of analytical transport model of MoS 2 tunnel field
effect transistor (TFET) using Verilog-A in Cadence/Spectre. The parameters of the model …
effect transistor (TFET) using Verilog-A in Cadence/Spectre. The parameters of the model …
A novel planar architecture for heterojunction TFETs with improved performance and its digital application as an inverter
S Yang, H Lv, B Lu, S Yan, Y Zhang - IEEE Access, 2020 - ieeexplore.ieee.org
A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The
advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and …
advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and …
Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption
Present complementary metal–oxide–semiconductor (CMOS) technology with scaled
channel lengths exhibits higher energy consumption in designing secure electronic circuits …
channel lengths exhibits higher energy consumption in designing secure electronic circuits …
[書籍][B] Architectural Support and Modeling of Emerging Technologies for Datacenter Privacy and Security Applications
AO Glova - 2022 - search.proquest.com
As computing continues to be used for increasingly private and sensitive operations
impacting all aspects of our lives, the need to maintain tight control of those computations …
impacting all aspects of our lives, the need to maintain tight control of those computations …
Low-power Microcontroller Units Design and Realization Using Emerging Tunneling Field Effect Transistors
H CAI, X TONG, J YANG - 电子与信息学报, 2024 - jeit.ac.cn
Abstract Tunneling Field Effect Transistor (TFET)-based low-power microcontroller design
combines devices, circuits, and systems to achieve extremely low leakage power …
combines devices, circuits, and systems to achieve extremely low leakage power …
[書籍][B] Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS
NO Adesina - 2022 - search.proquest.com
Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated
circuits. Since there is an increasing market for low noise and high speed devices, PLLs are …
circuits. Since there is an increasing market for low noise and high speed devices, PLLs are …
[書籍][B] Resource Management in Manycore Architecture: 3D NoC to Embedded Systems
S Musavvir - 2022 - search.proquest.com
Manycore architecture exploits tremendous computation capability for highly parallelized
workloads and big data analysis. Manycore chip uses network-in-chip (NoC) to transfer …
workloads and big data analysis. Manycore chip uses network-in-chip (NoC) to transfer …