A survey on application map** strategies for network-on-chip design

PK Sahu, S Chattopadhyay - Journal of systems architecture, 2013‏ - Elsevier
Application map** is one of the most important dimensions in Network-on-Chip (NoC)
research. It maps the cores of the application to the routers of the NoC topology, affecting the …

Map** on multi/many-core systems: Survey of current and emerging trends

AK Singh, M Shafique, A Kumar, J Henkel - Proceedings of the 50th …, 2013‏ - dl.acm.org
The reliance on multi/many-core systems to satisfy the high performance requirement of
complex embedded software applications is increasing. This necessitates the need to …

Privacy and communication complexity

E Kushelvitz - SIAM Journal on Discrete Mathematics, 1992‏ - SIAM
Each of two parties P_X and P_Y holds an n-bit input, x and y, respectively. They wish to
privately compute the value of f(x,y). That is, P_X should not learn any additional information …

Heuristics for dynamic task map** in NoC-based heterogeneous MPSoCs

E Carvalho, N Calazans… - 18th IEEE/IFIP International …, 2007‏ - ieeexplore.ieee.org
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize
the" design crisis"(gap between silicon technology and actual SoC design capacity) and …

Communication-aware heuristics for run-time task map** on NoC-based MPSoC platforms

AK Singh, T Srikanthan, A Kumar, W Jigang - Journal of Systems …, 2010‏ - Elsevier
Efficient run-time map** of tasks onto Multiprocessor System-on-Chip (MPSoC) is very
challenging especially when new tasks of other applications are also required to be …

A sliding window approach to natural hand gesture recognition using a custom data glove

G Luzhnica, J Simon, E Lex… - 2016 IEEE symposium on …, 2016‏ - ieeexplore.ieee.org
This paper explores the recognition of hand gestures based on a data glove equipped with
motion, bending and pressure sensors. We selected 31 natural and interaction-oriented …

New heuristic algorithms for energy aware application map** and routing on mesh-based NoCs

S Tosun - Journal of Systems Architecture, 2011‏ - Elsevier
Ever shrinking technologies in VLSI era made it possible to place several IP (Intellectual
Property) blocks onto a single die. This technology improvement also brought the challenge …

Application map** using cuckoo search optimization with Lévy flight for NoC-based system

MJ Mohiz, NK Baloch, F Hussain, S Saleem… - IEEE …, 2021‏ - ieeexplore.ieee.org
Network on chip (NoC) is a promising communication infrastructure for multiple cores on a
chip to exchange data efficiently. In such NoC architecture, application map** is a process …

An efficient and cost effective application map** for network-on-chip using Andean condor algorithm

F Mehmood, NK Baloch, F Hussain, W Amin… - Journal of Network and …, 2022‏ - Elsevier
Advancement in very large scale integration (VLSI) technologies and the ever-shrinking size
of the transistors have led the semiconductor designers to create a multiprocessor system on …

Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs

Y Cheng, L Zhang, Y Han, X Li - IEEE Transactions on Very …, 2012‏ - ieeexplore.ieee.org
3-D technology that stacks silicon dies with through silicon vias (TSVs) is a promising
solution to overcome the interconnect scaling problem in giga-scale integrated circuits (ICs) …