Traditional Network-on-Chips (NoCs) employ simple arbitration strategies, such as round-
robin or oldest-first, to decide which packets should be prioritized in the network. This is …

Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-
core processors. The challenge is to develop policies and mechanisms that enable multiple …

On-chip shared memory is the primary paradigm for multi-core SoC designs and poses the
most critical challenges to their scalability. Choosing the appropriate coherence model for …

With increasing core counts and higher memory demands from applications, it is imperative
that networks-on-chip (NoCs) provide low-latency, power-efficient communication …

Across many architectures and parallel programming paradigms, collective communication
plays a key role in performance and correctness. Hardware support is necessary to prevent …

Server workloads benefit from execution on many-core processors due to their massive
request-level parallelism. A key characteristic of server workloads is the large instruction …

As the number of applications and programmable units in CMPs and MPSoCs increases, the
Network-on-Chip (NoC) encounters unpredictable, heterogeneous and time dependent …

Chip Multiprocessor Systems (CMPs) rely on a cache coherency protocol to maintain
memory access coherence between cached data and main memory. The Hammer …

Continuous improvements in integration scale have made major microprocessor vendors to
move to designs that integrate several processing cores on the same chip. Chip …

Randomized algorithms for approximating the number of perfect matchings in a graph are
considered. An algorithm that is a natural simplification of one suggested and analyzed …