Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents
practical approaches for design and validation, with hands-on advice to help working …

During the last decade, popular SMT solvers have been extended step-by-step with a wide
range of decision procedures for different theories. Some SMT solvers also support the user …

Hardware Trojans are a major concern for integrated circuits. All parts of the electronics
supply chain are vulnerable to this threat. Trojans can be inserted directly by a rogue …

Transaction-level modeling (TLM) is the most promising technique to deal with the
increasing complexity of modern embedded systems. However, modeling a complex system …

A formal methodology for system verification of system-on-chip (SoC) designs is proposed. It
ensures that system-level models are created that are sound abstractions of the concrete …

This paper presents a new Property-Driven Design (PDD) method that starts from an
abstract system model and integrates formal property checking early into a top-down design …

Today for System-on-Chips (SoCs) companies Electronic System Level (ESL) design is the
established approach. Abstraction and standardized communication interfaces based on …

Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing
hardware designs with acceptable latency and throughput. However, it is a complex …

In high-level design explorations, many useful optimizations transform a circuit into another
with different operating cycles for a better trade-off between performance and resource …

High-level synthesis (HLS) improves design productivity by replacing cycle-accurate
specifications with untimed or transaction-based specifications. Obtaining high-quality RTL …