Modular routing design for chiplet-based systems

J Yin, Z Lin, O Kayiran, M Poremba… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking
of an SoC into smaller" chiplets." A chiplet-based SoC design process has the promise to …

Gme: Gpu-based microarchitectural extensions to accelerate homomorphic encryption

K Shivdikar, Y Bao, R Agrawal, M Shen… - Proceedings of the 56th …, 2023 - dl.acm.org
Fully Homomorphic Encryption (FHE) enables the processing of encrypted data without
decrypting it. FHE has garnered significant attention over the past decade as it supports …

Review of chiplet-based design: system architecture and interconnection

Y Liu, X Li, S Yin - Science China Information Sciences, 2024 - Springer
Chiplet-based design, which breaks a system into multiple smaller dice (or “chiplets”) and
reassembles them into a new system chip through advanced packaging, has received …

Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling

S Bharadwaj, J Yin, B Beckmann… - 2020 57th ACM/IEEE …, 2020 - ieeexplore.ieee.org
Recent advances in die-stacking and 2.5 D chip integration technologies introduce in-
package network heterogeneities that can complicate the interconnect design. Integrating …

A scalable methodology for designing efficient interconnection network of chiplets

Y Feng, D **ang, K Ma - 2023 IEEE International Symposium …, 2023 - ieeexplore.ieee.org
The Chiplet methodology can accelerate VLSI system development and provide better
flexibility. However, it is not easy to build interconnection networks across multiple chiplets …

Energy-efficient networks-on-chip architectures: Design and run-time optimization

SK Mandal, A Krishnakumar, UY Ogras - Network-on-Chip Security and …, 2021 - Springer
Abstract Networks-on-Chip (NoC) architectures have become the mainstream
communication backbone of high-end processors and systems-on-chip (SoCs) after their …

An open-source platform for high-performance non-coherent on-chip communication

A Kurth, W Rönninger, T Benz… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
On-chip communication infrastructure is a central component of modern systems-on-chip
(SoCs), and it continues to gain importance as the number of cores, the heterogeneity of …

Routing algorithms in optimal degree four circulant networks based on relative addressing: Comparative analysis for networks-on-chip

EA Monakhova, OG Monakhov… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
The solution of the problem of organizing optimal communications in circulant networks of
degree four is considered. For a family of optimal circulant networks with the minimum …

A deep reinforcement learning framework for architectural exploration: A routerless NoC case study

TR Lin, D Penney, M Pedram… - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
Machine learning applied to architecture design presents a promising opportunity with broad
applications. Recent deep reinforcement learning (DRL) techniques, in particular, enable …

Themis: A network bandwidth-aware collective scheduling policy for distributed training of dl models

S Rashidi, W Won, S Srinivasan, S Sridharan… - Proceedings of the 49th …, 2022 - dl.acm.org
Distributed training is a solution to reduce DNN training time by splitting the task across
multiple NPUs (eg, GPU/TPU). However, distributed training adds communication overhead …