[書籍][B] Arithmetic circuits for DSP applications
PK Meher, T Stouraitis - 2017 - books.google.com
A comprehensive guide to the fundamental concepts, designs, and implementation
schemes, performance considerations, and applications of arithmetic circuits for DSP …
schemes, performance considerations, and applications of arithmetic circuits for DSP …
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems
We introduce the notion of two-valued digit (twit) as a binary variable that can assume one of
two different integer values. Posibits, or simply bits, in {0, 1} and negabits in {-1, 0} …
two different integer values. Posibits, or simply bits, in {0, 1} and negabits in {-1, 0} …
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
Most common uses of negatively weighted bits (negabits), normally assuming arithmetic
value− 1 (0) for logical 1 (0) state, are as the most significant bit of 2's-complement numbers …
value− 1 (0) for logical 1 (0) state, are as the most significant bit of 2's-complement numbers …
Efficient conversion technique from redundant binary to nonredundant binary representation
Redundant Binary (RB) to Two's Complement (TC) converter offers nonredundant
representation. However, the sign bit of TC representation has to be handled using …
representation. However, the sign bit of TC representation has to be handled using …
An efficient universal addition scheme for all hybrid-redundant representations with weighted bit-set encoding
Redundant and hybrid-redundant number representations are used extensively to speed up
arithmetic operations within general-purpose and special-purpose digital systems, with the …
arithmetic operations within general-purpose and special-purpose digital systems, with the …
Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RE transmitters
This paper presents a very high-speed delta-sigma modulator for achieving digital
generation of radio-frequency signals. About 68 dB of ACLR (adjacent channel leakage …
generation of radio-frequency signals. About 68 dB of ACLR (adjacent channel leakage …
Approach to the design of parity-checked arithmetic circuits
B Parhami - Conference Record of the Thirty-Sixth Asilomar …, 2002 - ieeexplore.ieee.org
Achieving fault tolerance via parity checking is attractive due to low overhead in storage and
interconnect. However, nonpreservation of parity during arithmetic operations makes it …
interconnect. However, nonpreservation of parity during arithmetic operations makes it …
Tight upper bounds on the minimum precision required of the divisor and the partial remainder in high-radix division
B Parhami - IEEE Transactions on Computers, 2003 - ieeexplore.ieee.org
Digit-recurrence binary dividers are sped up via two complementary methods: kee** the
partial remainder in redundant form and selecting the quotient digits in a radix higher than 2 …
partial remainder in redundant form and selecting the quotient digits in a radix higher than 2 …
Fully redundant decimal addition and subtraction using stored-unibit encoding
öööööDecimal computer arithmetic is experiencing a revived popularity, and there is quest
for high-performance decimal hardware units. Successful experiences on binary computer …
for high-performance decimal hardware units. Successful experiences on binary computer …
Redundant number system-based arithmetic circuits
G Jaberipur - Arithmetic Circuits for DSP Applications, 2017 - books.google.com
Carry propagation in radix-based number systems, like the conventional binary or decimal
number systems, is the main issue that slows down the arithmetic operations. The latency of …
number systems, is the main issue that slows down the arithmetic operations. The latency of …