A comparative study of sorting algorithms with FPGA acceleration by high level synthesis
Nowadays, sorting is an important operation for several real-time embedded applications. It
is one of the most commonly studied problems in computer science. It can be considered as …
is one of the most commonly studied problems in computer science. It can be considered as …
Parallel implementation of genetic algorithm on FPGA using Vivado high level synthesis
E Alqudah, A Jarrah - International Journal of Bio-Inspired …, 2020 - inderscienceonline.com
Genetic algorithm (GA) is one of most popular evolutionary search algorithms that simulates
natural selection of genetic evolution for searching solution to arbitrary engineering …
natural selection of genetic evolution for searching solution to arbitrary engineering …
Virtual symmetry reduction
EA Emerson, JW Havlicek… - … Fifteenth Annual IEEE …, 2000 - ieeexplore.ieee.org
We provide a general method for ameliorating state explosion via symmetry reduction in
certain asymmetric systems, such as systems with many similar, but not identical, processes …
certain asymmetric systems, such as systems with many similar, but not identical, processes …
Investigating performance losses in high-level synthesis for stencil computations
W Altoyan, JJ Alonso - 2020 IEEE 28th Annual International …, 2020 - ieeexplore.ieee.org
With the aid of few directives and canonical forms, high-level synthesis (HLS) tools allow
FPGA developers to describe their hardware designs in higher-level languages such as C or …
FPGA developers to describe their hardware designs in higher-level languages such as C or …
An efficient hardware implementation of timsort and mergesort algorithms using high level synthesis
Sorting algorithms are one of the most commonly used in computer science. They can be
seen as a pillar for some applications such as decision support systems, path planning, etc …
seen as a pillar for some applications such as decision support systems, path planning, etc …
Reducing OpenMP to FPGA round-trip times with predictive modelling
Recent works aimed at expanding the target offloading capabilities of OpenMP to FPGA
platforms. While enabling the easy construction of heterogeneous systems, the approach …
platforms. While enabling the easy construction of heterogeneous systems, the approach …
Fast, Accurate and Distributed Simulation of novel HPC systems incorporating ARM and RISC-V CPUs
The growing developments of HPC systems used in a plethora of domains (healthcare,
financial services, government and defense, energy) triggers an urgent demand for …
financial services, government and defense, energy) triggers an urgent demand for …
SoC implementation of a photovoltaic reconfiguration algorithm by exploiting a HLS-based architecture
The dynamic reconfiguration of photovoltaic arrays is a promising technique for reducing the
power drops due to partial shadowing. Some approaches for determining the optimal …
power drops due to partial shadowing. Some approaches for determining the optimal …
Reduced memory viterbi decoding for hardware-accelerated speech recognition
Large Vocabulary Continuous Speech Recognition systems require Viterbi searching
through a large state space to find the most probable sequence of phonemes that led to a …
through a large state space to find the most probable sequence of phonemes that led to a …
A Real Time Simulator of a PEV's On Board Battery Charger
T Gherman, D Petreus… - 2019 International Aegean …, 2019 - ieeexplore.ieee.org
This paper presents an FPGA based real time (RT) simulator for a Plug in Electrical Vehicle”
s (PEV) on board battery charger. Common values for the switching frequencies of the AC …
s (PEV) on board battery charger. Common values for the switching frequencies of the AC …