This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

A novel test vector compression/decompression technique is proposed for reducing the
amount of test data that must be stored on a tester and transferred to each core when testing …

A scan-based BIST scheme is presented which guarantees complete fault coverage with
very low hardware overhead. A probabilistic analysis shows that the output of an LFSR …

A new form of LFSR reseeding that provides higher encoding efficiency and hence greater
reduction in test data storage requirements is described. Previous forms of LFSR reseeding …

A new lossless test vector compression scheme is presented which combines linear
feedback shift register (LFSR) reseeding and statistical coding in a powerful way. Test …

This paper presents a low-overhead scheme for the built-in self-test (BIST) of circuits with
scan. Complete (100%) fault coverage is obtained without modifying the function logic and …

In this paper a new scheme for deterministic and mixed mode scan-based BIST is
presented. It relies on a new type of test pattern generator which resembles a programmable …

An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of
peripheral devices having parallel Scan registers coupled to a processor core, all within an …

57 ABSTRACT A parallel decompressor capable of concurrently generating in parallel
multiple portions of a deterministic partially Specified data vector is disclosed. The parallel …