Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications
N Paras, SS Chauhan - Microelectronic Engineering, 2019 - Elsevier
The concept of dual metal and double gate in Vertical TFET is presented to show the
improvement of DC as well as analog/RF device performance standards due to enhanced …
improvement of DC as well as analog/RF device performance standards due to enhanced …
A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications
N Paras, SS Chauhan - Microelectronic Engineering, 2019 - Elsevier
In this paper, we propose a novel germanium source based dual metal gate tunneling field
effect transistor (VGeDMG). Design of device effectively suppresses lateral tunneling current …
effect transistor (VGeDMG). Design of device effectively suppresses lateral tunneling current …
Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs
N Paras, SS Chauhan - Applied Physics A, 2019 - Springer
In this paper, we present a rigorous numerical simulation study on temperature sensitivity for
tunnel field effect transistor (TFET). The presented temperature sensitivity analysis is studied …
tunnel field effect transistor (TFET). The presented temperature sensitivity analysis is studied …
An analytical model of gate-all-around heterojunction tunneling FET
Y Guan, Z Li, W Zhang, Y Zhang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
A compact analytical drain current model considering the inversion layer and source
depletion is developed for the gate-all-around (GAA) heterojunction tunneling FET (H-TFET) …
depletion is developed for the gate-all-around (GAA) heterojunction tunneling FET (H-TFET) …
Demonstration of fin-tunnel field-effect transistor with elevated drain
In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The
proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its …
proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its …
Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET
In this work, we propose and investigate a new pocket‐based Si0. 55Ge0. 45/Si gate normal
tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with …
tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with …
Tunneling FET Calibration Issues: Sentaurus vs. Silvaco TCAD
In this paper, a comprehensive comparison of TFET simulations using two TCAD simulators,
Sentaurus and Silvaco TCAD, is presented. The comparison is fully cover various types of …
Sentaurus and Silvaco TCAD, is presented. The comparison is fully cover various types of …
SiGe Source-Based Epitaxial Layer-Encapsulated TFET and its Application as a Resistive Load Inverter
In this study, a SiGe source-based epitaxial layer-encapsulated TFET (SiGe source
ETLTFET) is developed, and the performance of the device is examined by optimizing …
ETLTFET) is developed, and the performance of the device is examined by optimizing …
A FinBOX Based Ge FinEHBTFET: Design and Investigation
In this work, we propose a Germanium Fin Buried Oxide (FinBOX) Fin Electron-Hole Bilayer
Tunnel FET (FBF-EHBTFET) structure. The proposed structure eliminates the gated …
Tunnel FET (FBF-EHBTFET) structure. The proposed structure eliminates the gated …
Design of Extended Channel Ge-source TFET for Low Power Applications
F Shokry, A Shaker, M Elsaid… - International Journal of …, 2020 - penerbit.uthm.edu.my
In this paper, a novel design of a TFET structure using Ge-source and extending a part of the
channel into the source is proposed. The DC performance is analyzed by evaluating the ON …
channel into the source is proposed. The DC performance is analyzed by evaluating the ON …