APOLLO: An automated power modeling framework for runtime power introspection in high-volume commercial microprocessors

Z **e, X Xu, M Walker, J Knebel… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Accurate power modeling is crucial for energy-efficient CPU design and runtime
management. An ideal power modeling framework needs to be accurate yet fast, achieve …

Voltage noise in multi-core processors: Empirical characterization and optimization opportunities

R Bertran, A Buyuktosunoglu, P Bose… - 2014 47th Annual …, 2014 - ieeexplore.ieee.org
Voltage noise characterization is an essential aspect of optimizing the shipped voltage of
high-end processor based systems. Voltage noise, ie Variations in the supply voltage due to …

AUDIT: Stress testing the automatic way

Y Kim, LK John, S Pant, S Manne… - 2012 45th Annual …, 2012 - ieeexplore.ieee.org
Sudden variations in current (large di/dt) can lead to significant power supply voltage droops
and timing errors in modern microprocessors. Several papers discuss the complexity …

Classification framework for analysis and modeling of physically induced reliability violations

D Rodopoulos, G Psychou, MM Sabry… - ACM Computing …, 2015 - dl.acm.org
Technology downscaling is expected to amplify a variety of reliability concerns in future
digital systems. A good understanding of reliability threats is crucial for the creation of …

Back to the future: Current-mode processor in the era of deeply scaled CMOS

Y Bai, Y Song, MN Bojnordi, A Shapiro… - … Transactions on Very …, 2015 - ieeexplore.ieee.org
This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise
alternative to static CMOS circuits in microprocessors, thereby improving the performance …

An analytical framework for estimating scale-out and scale-up power efficiency of heterogeneous manycores

J Ma, G Yan, Y Han, X Li - IEEE Transactions on Computers, 2015 - ieeexplore.ieee.org
Heterogeneous manycore architectures have shown to be highly promising to boost power
efficiency through two independent ways:(1) enabling massive thread-level parallelism …

Leveraging CPU electromagnetic emanations for voltage noise characterization

Z Hadjilambrou, S Das, MA Antoniades… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage
measurements through either on-package measurement points or on-chip dedicated …

Sensing CPU voltage noise through Electromagnetic Emanations

Z Hadjilambrou, S Das, MA Antoniades… - IEEE Computer …, 2017 - ieeexplore.ieee.org
This work proposes sensing CPU voltage noise through wireless electromagnetic (EM)
emanations from the CPU. Compared to previous voltage monitoring methodologies, this …

Compiler-directed power management for superscalars

J Haj-Yihia, YB Asher, E Rotem, A Yasin… - ACM Transactions on …, 2015 - dl.acm.org
Modern superscalar CPUs contain large complex structures and diverse execution units,
consuming wide dynamic power range. Building a power delivery network for the worst-case …

Performance of radiation hardening techniques under voltage and temperature variations

VS Veeravalli, A Steininger - 2013 IEEE aerospace conference, 2013 - ieeexplore.ieee.org
The effectiveness of the techniques to mitigate radiation particle hits in digital CMOS circuits
has been mainly studied under a given set of environmental conditions. This paper will …