The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse
and perform staging are known as dataflow, which directly impacts the performance and …

Computer architecture simulation tools are essential for implementing and evaluating new
ideas in the domain and can be useful for understanding the behavior of programs and …

Moving data through the memory hierarchy is a fundamental bottleneck that can limit the
performance of core algorithms of machine learning, such as convolutional neural networks …

Compilation techniques for nested-parallel applications that can adapt to hardware and
dataset characteristics are vital for unlocking the power of modern hardware. This paper …

Deep Neural Networks (DNNs) have revolutionized many aspects of our lives. The use of
DNNs is becoming ubiquitous, including in software for image recognition, speech …

While the cost of computation is an easy to understand local property, the cost of data
movement on cached architectures depends on global state, does not compose, and is hard …

For applications in worst-case execution time analysis and in security, it is desirable to
statically classify memory accesses into those that result in cache hits, and those that result …

Compilers often use performance models to decide how to optimize code. This is often
preferred over using hardware performance measurements, since hardware measurements …

Reducing the number of data accesses in memory hierarchy is of paramount importance on
modern computer systems. One of the key optimizations addressing this problem is loop …

Data movement limits program performance. This bottleneck is more significant in multi-
thread programs but more difficult to analyze, especially for multiple thread counts. For …