We present a novel partially synchronous system model, which augments the asynchronous
model by a (possibly unknown) bound Θ on the ratio of longest and shortest end-to-end …

Classic distributed computing abstractions do not match well the reality of digital logic gates,
which are the elementary building blocks of Systems-on-Chip (SoCs) and other Very Large …

We present the first implementation of a distributed clock generation scheme for Systems-on-
Chip that recovers from an unbounded number of arbitrary transient faults despite a large …

Today's hardware technology presents a new challenge in designing robust systems. Deep
submicron VLSI technology introduces transient and permanent faults that were never …

Due to their handshake-based flow control, asynchronous circuits generally do not suffer
from metastability issues as much as synchronous circuits do. We will show, however, that …

In this paper, we introduce the Asynchronous Bounded-Cycle (ABC) model, which
considerably relaxes the Theta-Model proposed by Le Lann and Schmid. The ABC model …

We present the first FPGA implementation of a distributed clock synchronization algorithm
with sub-nanosecond skews that can tolerate arbitrary faults of individual components. Each …

We propose a communication scheme for GALS systems with independent but
approximately synchronized clock sources, which guarantees high-speed metastability-free …

We present a novel approach for the on‐chip generation of a fault‐tolerant clock. Our
method is based on the hardware implementation of a tick synchronization algorithm from …

Fault-tolerant clocking schemes become inevitable when it comes to highly-reliable chip
designs. Because of the additional hardware overhead, existing solutions are considerably …