Low-complexity multiplierless constant rotators based on combined coefficient selection and shift-and-add implementation (CCSSI)

M Garrido, F Qureshi… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper presents a new approach to design multiplierless constant rotators. The
approach is based on a combined coefficient selection and shift-and-add implementation …

Multiplierless unity-gain SDF FFTs

M Garrido, R Andersson, F Qureshi… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this brief, we propose a novel approach to implement multiplierless unity-gain single-
delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by …

The constant multiplier FFT

M Garrido, P Malagón - … Transactions on Circuits and Systems I …, 2020 - ieeexplore.ieee.org
In this paper, we present a new fast Fourier transform (FFT) hardware architecture called
constant multiplier (CM) FFT. Whereas rotators in previous architectures must rotate among …

[CARTE][B] Multiple constant multiplication optimizations for field programmable gate arrays

M Kumm, P Zipf - 2016 - Springer
As silicon technology advances, field programmable gate arrays appear to gain ground
against the traditional ASIC project starts, reaching out to form the mainstream …

Hierarchical design of an application-specific instruction set processor for high-throughput and scalable FFT processing

X Guan, Y Fei, H Lin - IEEE Transactions on Very Large Scale …, 2011 - ieeexplore.ieee.org
Fast Fourier transformation (FFT), a kernel data processing task in communication systems,
has been studied intensively for efficient software and hardware implementations …

Low-complexity reconfigurable complex constant multiplication for FFTs

F Qureshi, O Gustafsson - 2009 IEEE International Symposium …, 2009 - ieeexplore.ieee.org
In this work we consider structures for simultaneous multiplication by a small set of two
pairwise coefficients where the coefficients are the real and imaginary part of a limited …

Vlsi design of majority logic based wallace tree multiplier

S Jothimani, M Mugunthan - 2023 7th International …, 2023 - ieeexplore.ieee.org
By using the Wallace Tree multipliers architecture and improving the adder in each Wallace
Tree phase, reduce the unnecessary latency. The dominant logic primitive was used for …

Alternatives to reduce perfluorinated compound (PFC) emissions from semiconductor dielectric etch processes: Meeting environmental commitments while minimizing …

N Krishnan, R Smati, S Raoux… - … on Electronics and the …, 2003 - ieeexplore.ieee.org
Perfluorinated compounds (PFCs) are widely used in semiconductor processing. These inert
gases are used as a safe and efficient method to carry fluorine to etch and chemical vapor …

Low-power application-specific processor for FFT computations

TO Pitkänen, J Takala - Journal of Signal Processing Systems, 2011 - Springer
In this paper, a processor architecture tailored for radix-4 and mixed-radix FFT computations
is described. The processor has native support for power-of-two transform sizes. Several …

A satellite radio interface for IMT-Advanced system using OFDM

HW Kim, TC Hong, K Kang, BJ Ku… - … on Information and …, 2010 - ieeexplore.ieee.org
In this paper, we introduce a new satellite radio interface technology to provide efficient IMT-
Advanced services. Maximizing the commonalities with the terrestrial system is one of the …