Considerations for ultimate CMOS scaling
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
Emerging applications for high K materials in VLSI technology
RD Clark - Materials, 2014 - mdpi.com
The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI)
manufacturing for leading edge Dynamic Random Access Memory (DRAM) and …
manufacturing for leading edge Dynamic Random Access Memory (DRAM) and …
High-mobility Ge N-MOSFETs and mobility degradation mechanisms
Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several
different research groups in the past. The major mechanisms behind poor Ge NMOS …
different research groups in the past. The major mechanisms behind poor Ge NMOS …
The effect of donor/acceptor nature of interface traps on Ge MOSFET characteristics
In this paper, the acceptor and donor nature of interface traps are investigated using
conductance and interface trap time constant measurements on Ge n-and p-type metal …
conductance and interface trap time constant measurements on Ge n-and p-type metal …
III-V/Ge MOS device technologies for low power integrated systems
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the
promising devices for high performance and low power integrated systems in the future …
promising devices for high performance and low power integrated systems in the future …
High-Performance Ge nMOSFETs With Junctions Formed by “Spin-On Dopant”
We report high-mobility Ge nMOSFETs using a simple approach to form n+-p junctions by
rapid thermal diffusion of" spin-on dopant" to avoid implantation damage. These junctions …
rapid thermal diffusion of" spin-on dopant" to avoid implantation damage. These junctions …
Germanium nMOSFETs with recessed channel and S/D: Contact, scalability, interface, and drain current exceeding 1 A/mm
A novel recessed channel and source/drain (S/D) technique is employed in Ge nMOSFETs,
which greatly improves metal contacts to n-type Ge with contact resistance of down to 0.23 …
which greatly improves metal contacts to n-type Ge with contact resistance of down to 0.23 …
High FET Performance for a Future CMOS -Based Technology
F Bellenger, B De Jaeger, C Merckling… - IEEE Electron …, 2010 - ieeexplore.ieee.org
In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality
interfacial layer prior to high-¿ deposition is required to achieve low interface state densities …
interfacial layer prior to high-¿ deposition is required to achieve low interface state densities …
Improved Electrical Characteristics of Ge MOS Devices With High Oxidation State in Interfacial Layer Formed by In Situ Desorption
CC Li, KS Chang-Liao, LJ Liu, TM Lee… - IEEE electron device …, 2014 - ieeexplore.ieee.org
Ge MOS devices with about 95% Ge 4+ in HfGeO x interfacial layer are obtained by H 2 O
plasma process together with in situ desorption before atomic layer deposition (ALD). The …
plasma process together with in situ desorption before atomic layer deposition (ALD). The …
Fully depleted Ge CMOS devices and logic circuits on Si
We systematically studied Ge CMOS devices and logic circuits fabricated on a GeOI
substrate, with the novel recessed channel and source/drain structures. Various channel …
substrate, with the novel recessed channel and source/drain structures. Various channel …