For parallelism to become tractable for mass programmers, shared-memory languages and
environments must evolve to enforce disciplined practices that ban" wild shared-memory …

Modern and future many-core systems represent complex architectures. The communication
fabrics of these large systems heavily influence their performance and power consumption …

Growing core counts have highlighted the need for scalable on-chip coherence
mechanisms. The increase in the number of on-chip cores exposes the energy and area …

Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain
cache coherence. However, previously proposed coherence directories are hard to scale …

The cost of moving and storing data is still a fundamental concern for computer architects.
Inefficient handling of data can be attributed to conventional architectures being oblivious to …

An important challenge in multicore processors is the maintenance of cache coherence in a
scalable manner. Directory-based protocols save bandwidth and achieve scalability by …

Cache coherence is ubiquitous in shared memory multiprocessors because it provides a
simple, high performance memory abstraction to programmers. Recent work suggests …

Chip-multiprocessors require a coherence directory to track data sharing and order
accesses to the shared data. Scaling coherence directories to support a large number of …

Many core chips are emerging as the architecture of choice to provide power efficiency and
improve performance, while riding Moore's Law. In these architectures, on-chip inter …

Designing massive scale cache coherence systems has been an elusive goal. Whether it be
on large-scale GPUs, future thousand-core chips, or across million-core warehouse scale …