Testing of Integrated Circuits is important to ensure the production of fault-free chips.
However, testing is becoming cumbersome and expensive due to the increasing complexity …

Given a system-on-chip with a set of cores and a set of test resources, and the constraints on
the total power consumption during test and the maximum width on the top-level test access …

This paper describes a hybrid BIST solution for testing systems-on-chip which combines
pseudorandom test patterns with stored deterministic test patterns. A method is proposed to …

This paper presents a hybrid BIST architecture and methods for optimizing it to test system-
on-chip in a cost effective way. The proposed self-test architecture can be implemented …

This paper presents a solution to the test time minimization problem for core-based systems.
We assume a hybrid BIST approach, where a test set is assembled, for each core, from …

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test
equipment (ATE), and presents closed-form expressions for fault coverage as a function of …

This paper proposes a comprehensive model for test planning in a core-based environment.
The main contribution of this work is the use of several types of TAMs and the consideration …

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing,
and using linear feedback shift registers (LFSR) for test set generation and test response …

This paper analyzes an environment which utilizes Built-In Self-Test (BIST) and Automatic
Test Equipment (ATE), to reduce the overall time for manufacturing test of complex digital …

This paper presents a solution to the test tone minimization problem for core-based systems
that contain sequential cores with STUMPS architecture. We assume a hybrid BIST …