In this paper we propose an efficient hardware architecture that implements the Q-Learning
algorithm, suitable for real-time applications. Its main features are low-power, high …

Low-complexity and high-performance low-density parity-check (LDPC) decoders are highly
demanded in various modern communication and storage systems. In this paper, a novel …

This paper deals with the hardware implementation of the recently introduced Probabilistic
Gradient-Descent Bit-Flip** (PGDBF) decoder. The PGDBF is a new type of hard-decision …

The Gallager B (GaB), among the hard-decision class of low-density-parity-check (LDPC)
algorithms, is an ideal candidate for designing high-throughput decoder hardware …

Probabilistic gradient descent bit-flip** (PGDBF) is a hard-decision decoder for low-
density parity-check (LDPC) codes, which offers a significant improvement in error …

This paper presents a new bit flip** (BF) decoder, called the probabilistic parallel BF
(PPBF) for low-density parity-check codes on the binary symmetric channel. In the PPBF, the …

This work presents a compact CMOS Image Sensor (CIS) architecture enabling embedded
object recognition facilitated by a dedicated end-of-column Compressive Sensing (CS) …

An error floor phenomenon, decoding performance, and throughput are three major
concerns for LDPC decoders in NAND Flash applications. With a penalty method and an …

Double Q-Learning (DQL) is an off-policy reinforcement learning algorithm providing better
performance in a stochastic environment compared to the Q-Learning technique. This paper …

Existing bit-flip** algorithms, when used for irregular low-density parity-check (LDPC)
codes, often suffer from performance degradation due to the imbalance caused by the …