Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering
An experimental study is presented to compare two different schemes used to incorporate a
high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, ie, dopant …
high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, ie, dopant …
High-performance FinFET with dopant-segregated Schottky source/drain
A Kaneko, A Yagishita, K Yahashi… - 2006 International …, 2006 - ieeexplore.ieee.org
High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-
Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in …
Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in …
Ultra low voltage operations in bulk CMOS logic circuits with dopant segregated Schottky source/drain transistors
T Kinoshita, R Hasumi, M Hamaguchi… - 2006 International …, 2006 - ieeexplore.ieee.org
Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS)
source/drain transistors for the first time. DSS greatly improves propagation delay in multiple …
source/drain transistors for the first time. DSS greatly improves propagation delay in multiple …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Challenges of 22 nm and beyond CMOS technology
R Huang, HM Wu, JF Kang, DY **ao, XL Shi… - Science in China Series …, 2009 - Springer
It is predicted that CMOS technology will probably enter into 22 nm node around 2012.
Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and …
Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Method for fabrication of a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …