Spatial memory streaming

S Somogyi, TF Wenisch, A Ailamaki, B Falsafi… - ACM SIGARCH …, 2006 - dl.acm.org
Prior research indicates that there is much spatial variation in applications' memory access
patterns. Modern memory systems, however, use small fixed-size cache blocks and as such …

Managing multi-configuration hardware via dynamic working set analysis

AS Dhodapkar, JE Smith - ACM SIGARCH Computer Architecture News, 2002 - dl.acm.org
Microprocessors are designed to provide good average performance over a variety of
workloads. This can lead to inefficiencies both in power and performance for individual …

A highly configurable cache architecture for embedded systems

C Zhang, F Vahid, W Najjar - … of the 30th annual international symposium …, 2003 - dl.acm.org
Energy consumption is a major concern in many embedded computing systems. Several
studies have shown that cache memories account for about 50% of the total energy …

A survey on cache tuning from a power/energy perspective

W Zang, A Gordon-Ross - ACM Computing Surveys (CSUR), 2013 - dl.acm.org
Low power and/or energy consumption is a requirement not only in embedded systems that
run on batteries or have limited cooling capabilities, but also in desktop and mainframes …

CHOP: Adaptive filter-based DRAM caching for CMP server platforms

X Jiang, N Madan, L Zhao, M Upton… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
As manycore architectures enable a large number of cores on the die, a key challenge that
emerges is the availability of memory bandwidth with conventional DRAM solutions. To …

Adaptive granularity memory systems: A tradeoff between storage efficiency and throughput

DH Yoon, MK Jeong, M Erez - Proceedings of the 38th annual …, 2011 - dl.acm.org
We propose adaptive granularity to combine the best of fine-grained and coarse-grained
memory accesses. We augment virtual memory to allow each page to specify its preferred …

Accurate and complexity-effective spatial pattern prediction

CF Chen, SH Yang, B Falsafi… - … Symposium on High …, 2004 - ieeexplore.ieee.org
Recent research suggests that there are large variations in a cache's spatial usage, both
within and across programs. Unfortunately, conventional caches typically employ fixed …

A self-tuning cache architecture for embedded systems

C Zhang, F Vahid, R Lysecky - ACM Transactions on Embedded …, 2004 - dl.acm.org
Memory accesses often account for about half of a microprocessor system's power
consumption. Customizing a microprocessor cache's total size, line size, and associativity to …

Performance and power optimization through data compression in network-on-chip architectures

R Das, AK Mishra, C Nicopoulos, D Park… - 2008 IEEE 14th …, 2008 - ieeexplore.ieee.org
The trend towards integrating multiple cores on the same die has accentuated the need for
larger on-chip caches. Such large caches are constructed as a multitude of smaller cache …

Amoeba-cache: Adaptive blocks for eliminating waste in the memory hierarchy

S Kumar, H Zhao, A Shriraman… - 2012 45th Annual …, 2012 - ieeexplore.ieee.org
The fixed geometries of current cache designs do not adapt to the working set requirements
of modern applications, causing significant inefficiency. The short block lifetimes and …