A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches

S Mittal, JS Vetter, D Li - IEEE Transactions on Parallel and …, 2014 - ieeexplore.ieee.org
Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large
increase in the size of on-chip caches. Since SRAM has low density and consumes large …

Data allocation optimization for hybrid scratch pad memory with SRAM and nonvolatile memory

J Hu, CJ Xue, Q Zhuge, WC Tseng… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Embedded systems normally have a tight energy budget. Since the on-chip cache typically
consumes 25%-50% of the processor's area and energy consumption, scratch pad memory …

Prediction hybrid cache: An energy-efficient STT-RAM cache architecture

J Ahn, S Yoo, K Choi - IEEE Transactions on Computers, 2015 - ieeexplore.ieee.org
Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density
alternative to SRAM for large on-chip caches. However, its high write energy has been …

AYUSH: A technique for extending lifetime of SRAM-NVM hybrid caches

S Mittal, JS Vetter - IEEE Computer Architecture Letters, 2014 - ieeexplore.ieee.org
Recently, researchers have explored way-based hybrid SRAM-NVM (non-volatile memory)
last level caches (LLCs) to bring the best of SRAM and NVM together. However, the limited …

Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems

Q Li, J Li, L Shi, M Zhao, CJ Xue… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
Hybrid caches consisting of static RAM (SRAM) and spin-torque transfer (STT)-RAM have
been proposed recently for energy efficiency. To explore the advantages of hybrid cache …

NVM way allocation scheme to reduce NVM writes for hybrid cache architecture in chip-multiprocessors

JH Choi, GH Park - IEEE Transactions on Parallel and …, 2017 - ieeexplore.ieee.org
Hybrid cache architectures (HCAs) containing both SRAM and non-volatile memory (NVM)
have been proposed to overcome the disadvantages of NVM-based cache architecture …

DR. Swap: Energy-efficient paging for smartphones

K Zhong, X Zhu, T Wang, D Zhang, X Luo… - Proceedings of the …, 2014 - dl.acm.org
Smartphones are becoming increasingly energy-hungry to support feature-rich applications,
posing a lot of pressure on battery lifetime and making energy consumption a non-negligible …

Compiler directed write-mode selection for high performance low power volatile PCM

Q Li, L Jiang, Y Zhang, Y He, CJ Xue - Proceedings of the 14th ACM …, 2013 - dl.acm.org
Micro-Controller Units (MCUs) are widely adopted ubiquitous computing devices. Due to
tight cost and energy constraints, MCUs often integrate very limited internal RAM memory on …

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh

J Li, L Shi, Q Li, CJ Xue, Y Chen, Y Xu… - ACM Transactions on …, 2013 - dl.acm.org
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement
because of its excellent features, such as fast read access, high density, low leakage power …

Hybrid nonvolatile disk cache for energy-efficient and high-performance systems

L Shi, J Li, C Jason Xue, X Zhou - ACM Transactions on Design …, 2013 - dl.acm.org
NAND flash memory has been employed as disk cache in recent years. It has the
advantages of high performance, low leakage power, and cost efficiency. However, flash …