Despite vast research on defenses to protect stack objects from the exploitation of memory
errors, much stack data remains at risk. Historically, stack defenses focus on the protection of …

We present our compiler intermediate representation FIRM. Programs are always in SSA-
form enabling a concise graph-based representation. We argue that this naturally encodes …

Register allocation is a well-studied problem, but surprisingly little work has been published
on assigning registers for GPU architectures. In this paper we present the register allocator …

Register allocation is a crucial step in the compilation pipeline that decides what program
values occupy which physical registers. Single-path code's use of predicated instructions …

Graph coloring and linear scan are two appealing techniques for register allocation as the
underlying formalism are extremely clean and simple. This paper advocates a decoupled …

Recent developments in register allocation, mostly linked to static single assignment (SSA)
form, have shown the benefits of decoupling the problem in two phases: a first spilling phase …

The integrated approaches for instruction scheduling and register allocation have been
promising area of research for code generation and compiler optimization. In this paper we …

This paper deals with coalescing in SSA-based register allocation. Current coalescing
techniques all require the interference graph to be built. This is generally considered to be …

Sažetak High performance, low power multiprocessor/multibank memory system requires a
compiler that provides efficient data partitioning and map** procedures. This paper …

Compilers use software-controlled local memories to provide fast, predictable, and power-
efficient access to critical data. We show that the local memory allocation for straight-line, or …