A survey on pipelined FFT hardware architectures

M Garrido - Journal of Signal Processing Systems, 2022‏ - Springer
The field of pipelined FFT hardware architectures has been studied during the last 50 years.
This paper is a survey that includes the main advances in the field related to architectures for …

A new representation of FFT algorithms using triangular matrices

M Garrido - IEEE Transactions on Circuits and Systems I …, 2016‏ - ieeexplore.ieee.org
In this paper we propose a new representation for FFT algorithms called the triangular matrix
representation. This representation is more general than the binary tree representation and …

The serial commutator FFT

M Garrido, SJ Huang, SG Chen… - IEEE Transactions on …, 2016‏ - ieeexplore.ieee.org
This brief presents a new type of fast Fourier transform (FFT) hardware architectures called
serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit …

Multiplierless unity-gain SDF FFTs

M Garrido, R Andersson, F Qureshi… - IEEE Transactions on …, 2016‏ - ieeexplore.ieee.org
In this brief, we propose a novel approach to implement multiplierless unity-gain single-
delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by …

48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches

XY Shih, YQ Liu, HR Chou - … on Circuits and Systems I: Regular …, 2017‏ - ieeexplore.ieee.org
In this paper, we propose a reconfigurable (RC) fast Fourier transform (FFT) design in a
systematic design scheme. The RC design bricks are mainly proposed to arbitrarily …

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

GK Ganjikunta, SK Sahoo - Integration, 2017‏ - Elsevier
In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast
Fourier Transform (FFT) is a critical block as it occupies large area and consumes more …

Design and implementation of flexible and reconfigurable SDF-based FFT chip architecture with changeable-radix processing elements

XY Shih, HR Chou, YQ Liu - … on Circuits and Systems I: Regular …, 2018‏ - ieeexplore.ieee.org
In this paper, we propose a flexible and reconfigurable changeable-radix fast Fourier
transform (FFT) hardware architecture. It aims to support 48 different FFT sizes and up to …

Evolution of the performance of pipelined FFT architectures through the years

M Garrido - 2020 XXXV Conference on Design of Circuits and …, 2020‏ - ieeexplore.ieee.org
This paper explores the evolution of the three main figures of merit for pipeline fast Fourier
transform (FFT) architecture through the years. These figures of merit are throughput, power …

Radix-8 FFT processor design based on FPGA

M Sun, L Tian, D Dai - 2012 5th International Congress on …, 2012‏ - ieeexplore.ieee.org
A design of 4096-point radix-8 fast Fourier transform (FFT) is implemented on Field
Programming Gate Array (FPGA). The butterfly element, twiddle factor generator, I/O unit …

FFT hardware architectures with reduced twiddle factor sets

R Andersson - 2013‏ - diva-portal.org
The goal of this thesis has been to reduce the hardware cost of SDF FFTs. In order to
achieve this, two methods for simplifying rotations in FFTs are presented: Decimation and …