Advances in the atomic force microscopy for critical dimension metrology

D Hussain, K Ahmad, J Song… - Measurement Science and …, 2016 - iopscience.iop.org
Downscaling, miniaturization and 3D staking of the micro/nano devices are burgeoning
phenomena in the semiconductor industry which have posed sophisticated challenges in …

Impact of process variation on nanosheet gate-all-around complementary FET (CFET)

X Yang, X Li, Z Liu, Y Sun, Y Liu, X Li… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA)
complementary FET (CFET) induced by process fluctuations are investigated for the first …

Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part II–experimental results and impacts on device …

R Wang, X Jiang, T Yu, J Fan, J Chen… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …

Impact of fin line edge roughness and metal gate granularity on variability of 10-nm node SOI n-FinFET

A Sudarsanan, S Venkateswarlu… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi
Fin n-FET due to the impact of random fluctuation sources such as gate work function …

3-D LER and RDF matching performance of nanowire FETs in inversion, accumulation, and junctionless modes

AK Bansal, C Gupta, A Gupta, R Singh… - … on Electron Devices, 2018 - ieeexplore.ieee.org
Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for
realization of advanced CMOS technology nodes. Due to small nanowire dimensions …

Impact of process fluctuations on reconfigurable silicon nanowire transistor

X Li, X Yang, Z Zhang, T Wang, Y Sun… - … on Electron Devices, 2021 - ieeexplore.ieee.org
In this article, the impact of intrinsic process fluctuations on reconfigurable field-effect
transistor (RFET) is investigated for the first time. Three kinds of process fluctuation sources …

Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect transistor

RG Debnath, S Baishya - Microelectronics Journal, 2022 - Elsevier
A simulation study of the impact of interface traps on the performance of the Epitaxial Layer
Tunnel Field Effect Transistor (ETLTFET) having Si (1-x) Ge x as source material is …

Line-edge roughness from extreme ultraviolet lithography to fin-field-effect-transistor: computational study

SK Kim - Micromachines, 2021 - mdpi.com
Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch
resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line …

A device-level characterization approach to quantify the impacts of different random variation sources in FinFET technology

X Jiang, S Guo, R Wang, X Wang… - IEEE electron device …, 2016 - ieeexplore.ieee.org
A simple device-level characterization approach to quantitatively evaluate the impacts of
different random variation sources in FinFETs is proposed. The impacts of random dopant …

Nanosized-Metal-Grain-Pattern-Dependent Threshold-Voltage Models for the Vertically Stacked Multichannel Gate-All-Around Si Nanosheet MOSFETs and Their …

WL Sung, Y Li, MH Chuang - IEEE Transactions on Electron …, 2023 - ieeexplore.ieee.org
This article proposes grain-pattern-dependent threshold-voltage () models to predict the
variability of () due to work-function (WK) fluctuation (WKF) for the vertically stacked …