Downscaling, miniaturization and 3D staking of the micro/nano devices are burgeoning
phenomena in the semiconductor industry which have posed sophisticated challenges in …

In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA)
complementary FET (CFET) induced by process fluctuations are investigated for the first …

In the part I of this paper, the correlation between line-edge roughness (LER) and line-width
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi
Fin n-FET due to the impact of random fluctuation sources such as gate work function …

Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for
realization of advanced CMOS technology nodes. Due to small nanowire dimensions …

In this work, a semi-analytical compact model of random process fluctuations in nanosheet
(NS) gate-all-around (GAA) complementary FET (CFET) is proposed, including work …

A simulation study of the impact of interface traps on the performance of the Epitaxial Layer
Tunnel Field Effect Transistor (ETLTFET) having Si (1-x) Ge x as source material is …

In this article, the impact of intrinsic process fluctuations on reconfigurable field-effect
transistor (RFET) is investigated for the first time. Three kinds of process fluctuation sources …

Variabilities such as threshold voltage, on-current, and subthreshold swing due to random
dopant fluctuation (RDF), work function variation (WFV), and line edge roughness (LER) are …

Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch
resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line …