In the late-CMOS era, semiconductor and electronics companies face severe product
schedule and other competitive pressures. In this context, electronic design automation …

Timing closure is the most critical phase of modern system-on-chip implementation: without
timing closure, there is no tapeout. Timing closure is the end result of (i) years of …

Placement is central to IC physical design: it determines spatial embedding, and hence
parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized …

Design-based equivalent scaling now bears much of the burden of continuing the
semiconductor industry's trajectory of Moore's-Law value scaling. In the future, reductions of …

Concurrent Clock and Data (CCD) optimization is a well-adopted approach in modern
commercial tools that resolves timing violations using a mixture of clock skewing and delay …

Incremental timing-driven placement (TDP) is one of the most crucial steps for timing closure
in a physical design. The need for high-performance incremental TDP continues to grow, but …

Power consumption has become a major constraint in VLSI design. A considerable power
increase is usually seen during the hold closure step of the physical design done in post …

Physical synthesis is a fundamental part of the design flow of the modern VLSI since it
transforms automatically the designer's RTL models to an integrated circuit ready for …

Managing the timing constraints has become an important factor in the physical design of
multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module …

Skew optimization is an important stage of the physical design. Previous studies suggested
various skew optimization algorithms [1-7]. However, many of them have only focused on the …