A modified Gradient Descent Bit Flip** (GDBF) algorithm is proposed for decoding Low
Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise …

We analyze the performance of quantized min-sum decoding of low-density parity-check
codes under unreliable message storage. To this end, we introduce a simple bit-level error …

This paper studies the performance of a noisy Gallager B decoder for regular LDPC codes.
We assume that the noisy decoder is subject to both transient processor errors and …

This paper investigates the behavior of the Min-Sum decoder running on noisy devices. Our
aim is to evaluate the robustness of the decoder to computation noise caused by the faulty …

The wide recognition that emerging nano-devices will be inherently unreliable motivates the
evaluation of information processing algorithms running on noisy hardware as well as the …

This paper addresses the problem of designing low-density parity check decoders robust to
transient errors introduced by faulty hardware. We assume that the faulty hardware …

This paper proposes a “quasi-synchronous” design approach for signal processing circuits,
in which timing violations are permitted, but without the need for a hardware compensation …

In this paper, we investigate the decoding performance of spatially-coupled LDPC codes in
the case of faulty memory bit-cells within the storage modules of the decoder. Our study …

This paper proposes an FPGA based flooded architecture for quasi-cyclic (QC) LDPC
decoder. The message computation for both check and variable node update is done using …

We propose an improved version of probabilistic gradient descent bit flip** algorithm for
decoding low density parity check codes, based on MUltiple Decoding attempts and …