P2C2: Programmable pixel compressive camera for high speed imaging

D Reddy, A Veeraraghavan, R Chellappa - CVPR 2011, 2011 - ieeexplore.ieee.org
We describe an imaging architecture for compressive video sensing termed programmable
pixel compressive camera (P2C2). P2C2 allows us to capture fast phenomena at frame rates …

Adaptive contention management for fine-grained synchronization on commodity GPUs

L Gao, J Wang, W Zhang - ACM Transactions on Architecture and Code …, 2022 - dl.acm.org
As more emerging applications are moving to GPUs, fine-grained synchronization has
become imperative. However, their performance can be severely impaired in case of …

A machine learning-based approach for thread map** on transactional memory applications

M Castro, LFW Goes, CP Ribeiro… - … Conference on High …, 2011 - ieeexplore.ieee.org
Thread map** has been extensively used as a technique to efficiently exploit memory
hierarchy on modern chip-multiprocessors. It places threads on cores in order to amortize …

Seer: Probabilistic scheduling for hardware transactional memory

N Diegues, P Romano, S Garbatov - ACM Transactions on Computer …, 2017 - dl.acm.org
The ubiquity of multicore processors has led programmers to write parallel and concurrent
applications to take advantage of the underlying hardware and speed up their executions. In …

Transactional scheduling for read-dominated workloads

H Attiya, A Milani - Journal of Parallel and Distributed Computing, 2012 - Elsevier
The transactional approach to contention management guarantees atomicity by aborting
transactions that may violate consistency. A major challenge in this approach is to schedule …

Bloom filter guided transaction scheduling

G Blake, RG Dreslinski, T Mudge - 2011 IEEE 17th …, 2011 - ieeexplore.ieee.org
Contention management is an important design component to a transactional memory
system. Without effective contention management to ensure forward progress, a …

Analytical/ML mixed approach for concurrency regulation in software transactional memory

D Rughetti, P Di Sanzo, B Ciciani… - 2014 14th IEEE/ACM …, 2014 - ieeexplore.ieee.org
In this article we exploit a combination of analytical and Machine Learning (ML) techniques
in order to build a performance model allowing to dynamically tune the level of concurrency …

An improved layout verification algorithm (LAVA)

MS Abadir, J Ferguson - Proceedings of the European Design …, 1990 - computer.org
Abstract Conventional Transactional Memory (TM) systems may experience performance
degradation in applications with high contention, given the fact that execution of transaction …

The velox transactional memory stack

Y Afek, U Drepper, P Felber, C Fetzer, V Gramoli… - IEEE micro, 2010 - ieeexplore.ieee.org
The adoption of multi-and many-core architectures for mainstream computing undoubtedly
brings profound changes in the way software is developed. In particular, the use of fine …

F2c2-stm: Flux-based feedback-driven concurrency control for stms

K Ravichandran, S Pande - 2014 IEEE 28th International …, 2014 - ieeexplore.ieee.org
Software Transactional Memory (STM) systems provide an easy to use programming model
for concurrent code and have been found suitable for parallelizing many applications …