This paper aims at designing a digital approach based low jitter, smaller area and wide
frequency range phase locked loop (PLL) to reduce the design efforts and power which can …

A precharged CMOS high-performance phase frequency detector (PFD) circuit is presented
in this paper. The PFD consists of two identical building blocks. Each PFD block generates …

In this paper, some building blocks of the conventional delay-locked-loops are modified to
achieve a higher frequency range and smaller jitter on generated phases. A novel sensitive …

There is an urgent need for high-quality and high-frequency clock generators for high-
energy physics experiments. The transmission data rate exceeds 10 Gbps for a single …

Conventional structure of delay locked loops (DLLs) is modified to achieve better jitter and
smaller lock time. In the proposed structure, analog charge pump is eliminated, to remove …

A digital calibration scheme is proposed to reduce the systematic jitter due to the periodic
current leakage in charge pump phase-locked loops. Frequency acquisition is performed …

In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a
Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10 …

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled
oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL …

This article presents development and implementation of an integer N-type Phase Locked
Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise …

A direct divide-by-2/3 LC injection-locked frequency divider (ILFD) is presented in this paper.
The proposed ILFD circuit is based on a CMOS LC tank oscillator coupled with an injection …